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[src/netbsd-8]: src/sys/dev/pci Pull up the following revisions, requested by...
details: https://anonhg.NetBSD.org/src/rev/8fec4c95c452
branches: netbsd-8
changeset: 1026632:8fec4c95c452
user: martin <martin%NetBSD.org@localhost>
date: Fri Dec 03 19:45:13 2021 +0000
description:
Pull up the following revisions, requested by msaitoh in ticket #1714:
sys/dev/pci/pcireg.h 1.148-1.154, 1.156-1.161
sys/dev/pci/pci_subr.c 1.217-1.222, 1.224, 1.227-1.232
via patch
sys/dev/pci/nvme_pci.c 1.31
sys/dev/pci/pci.c 1.158
sys/dev/pci/ppb.c 1.74
- Print Bridge Config Retry Enable bit and Retimer Presence Detect
Supported bit.
- Add PCIe 4.0 stuff a little:
- 10-bit Tag Requester/Completer.
- Add Data link Feature extended capability.
- Add Physical Layer 16.0 GT/s extended capability. Not decode yet.
- Change pci_conf_print() to allocate memory for the regs dynamically
instead of on-stack.
- Print some DPC register values not with %04x but with %08x because
those are 32bit.
- Fix a bug that the virtual channel extended configuration's
arbitration phase register can't be decoded correctly.
- When parsing Enhanced Allocation entries, use the correct calculation
for finding the next entry.
- Add 32.0GT/s to the list of pcie speeds (PCIe 5.x.).
- Add Some PCI config information:
- Lane Margining at the Receiver
- NVME admin interface
- UFSHCI
- InfiniBand
- Host fabric
- HDA 1.0 with vendor ext
- USB4 HCI
- MIPI I3C
- Cellular controller/modem (+ Ethernet)
- Change PCI_VENDOR_MASK and PCI_PRODUCT_MASK to unsigned values, to
prevent sign extension of product ID when shifted up into place in
PCI_ID_CODE(). Fixes PR kern/56176.
- Add LCAP & LCAP2 definitions.
- Use PCI-SIG official acronyms for some macros.
- Remove unused shift and mask definitions.
- Fix typo in some messages.
- Fix typo in comments.
- Whitespace fixes.
diffstat:
sys/dev/pci/nvme_pci.c | 6 +-
sys/dev/pci/pci_subr.c | 206 +++++++++++++++++++++++++++++++++---------------
sys/dev/pci/pcireg.h | 192 +++++++++++++++++++++++---------------------
sys/dev/pci/ppb.c | 8 +-
4 files changed, 246 insertions(+), 166 deletions(-)
diffs (truncated from 1072 to 300 lines):
diff -r d9b0f46a89bc -r 8fec4c95c452 sys/dev/pci/nvme_pci.c
--- a/sys/dev/pci/nvme_pci.c Fri Dec 03 19:31:19 2021 +0000
+++ b/sys/dev/pci/nvme_pci.c Fri Dec 03 19:45:13 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: nvme_pci.c,v 1.19.2.2 2019/01/27 18:35:19 martin Exp $ */
+/* $NetBSD: nvme_pci.c,v 1.19.2.3 2021/12/03 19:45:13 martin Exp $ */
/* $OpenBSD: nvme_pci.c,v 1.3 2016/04/14 11:18:32 dlg Exp $ */
/*
@@ -43,7 +43,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: nvme_pci.c,v 1.19.2.2 2019/01/27 18:35:19 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: nvme_pci.c,v 1.19.2.3 2021/12/03 19:45:13 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -133,7 +133,7 @@
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_NVM &&
- PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_NVM_NVME)
+ PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_NVM_NVME_IO)
return 1;
return 0;
diff -r d9b0f46a89bc -r 8fec4c95c452 sys/dev/pci/pci_subr.c
--- a/sys/dev/pci/pci_subr.c Fri Dec 03 19:31:19 2021 +0000
+++ b/sys/dev/pci/pci_subr.c Fri Dec 03 19:45:13 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.183.2.12 2019/09/26 18:14:54 martin Exp $ */
+/* $NetBSD: pci_subr.c,v 1.183.2.13 2021/12/03 19:45:13 martin Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.183.2.12 2019/09/26 18:14:54 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.183.2.13 2021/12/03 19:45:13 martin Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -52,6 +52,11 @@
#include <sys/systm.h>
#include <sys/intr.h>
#include <sys/module.h>
+#include <sys/kmem.h>
+
+#define MALLOC(sz) kmem_alloc(sz, KM_SLEEP)
+#define FREE(p, sz) kmem_free(p, sz)
+
#else
#include <pci.h>
#include <stdarg.h>
@@ -59,6 +64,10 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
+
+#define MALLOC(sz) malloc(sz)
+#define FREE(p, sz) free(p)
+
#endif
#include <dev/pci/pcireg.h>
@@ -120,7 +129,15 @@
static const struct pci_class pci_interface_nvm[] = {
{ "vendor specific", PCI_INTERFACE_NVM_VND, NULL, },
{ "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, },
- { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, },
+ { "NVMe I/O", PCI_INTERFACE_NVM_NVME_IO, NULL, },
+ { "NVMe admin", PCI_INTERFACE_NVM_NVME_ADMIN, NULL, },
+ { NULL, 0, NULL, },
+};
+
+/* UFS programming interface */
+static const struct pci_class pci_interface_ufs[] = {
+ { "vendor specific", PCI_INTERFACE_UFS_VND, NULL, },
+ { "UFSHCI", PCI_INTERFACE_UFS_UFSHCI, NULL, },
{ NULL, 0, NULL, },
};
@@ -138,6 +155,8 @@
{ "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, },
{ "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM,
pci_interface_nvm, },
+ { "UFS", PCI_SUBCLASS_MASS_STORAGE_UFS,
+ pci_interface_ufs, },
{ "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -154,6 +173,8 @@
{ "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, },
{ "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, },
{ "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, },
+ { "InfiniBand", PCI_SUBCLASS_NETWORK_INFINIBAND, NULL, },
+ { "Host fabric", PCI_SUBCLASS_NETWORK_HFC, NULL, },
{ "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -182,11 +203,20 @@
* Class 0x04.
* Multimedia device.
*/
+
+/* HD Audio programming interface */
+static const struct pci_class pci_interface_hda[] = {
+ { "HD Audio 1.0", PCI_INTERFACE_HDAUDIO, NULL, },
+ { "HD Audio 1.0 + vendor ext", PCI_INTERFACE_HDAUDIO_VND, NULL, },
+ { NULL, 0, NULL, },
+};
+
static const struct pci_class pci_subclass_multimedia[] = {
{ "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, },
{ "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, },
{ "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,},
- { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, },
+ { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO,
+ pci_interface_hda, },
{ "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -422,6 +452,7 @@
{ "OHCI", PCI_INTERFACE_USB_OHCI, NULL, },
{ "EHCI", PCI_INTERFACE_USB_EHCI, NULL, },
{ "xHCI", PCI_INTERFACE_USB_XHCI, NULL, },
+ { "USB4 HCI", PCI_INTERFACE_USB_USB4HCI, NULL, },
{ "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, },
{ "device", PCI_INTERFACE_USB_DEVICE, NULL, },
{ NULL, 0, NULL, },
@@ -451,6 +482,7 @@
pci_interface_ipmi, },
{ "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, },
{ "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, },
+ { "MIPI I3C", PCI_SUBCLASS_SERIALBUS_MIPI_I3C, NULL, },
{ "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -467,6 +499,8 @@
{ "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, },
{ "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, },
{ "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, },
+ { "Cellular", PCI_SUBCLASS_WIRELESS_CELL, NULL, },
+ { "Cellular + Ethernet", PCI_SUBCLASS_WIRELESS_CELL_E, NULL, },
{ "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -834,7 +868,7 @@
if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
reg = regs[o2i(pcie_capoff + PCIE_XCAP)];
- if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_ROOT_EVNTC)
+ if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_RC_EVNTC)
subclass = PCI_SUBCLASS_SYSTEM_RCEC;
}
}
@@ -1688,7 +1722,9 @@
}
}
-static const char * const pcie_linkspeeds[] = {"2.5", "5.0", "8.0", "16.0"};
+static const char * const pcie_linkspeeds[] = {
+ "2.5", "5.0", "8.0", "16.0", "32.0"
+};
/*
* Print link speed. This function is used for the following register bits:
@@ -1779,7 +1815,7 @@
printf("Legacy PCI Express Endpoint device\n");
check_upstreamport = true;
break;
- case PCIE_XCAP_TYPE_ROOT: /* 0x4 */
+ case PCIE_XCAP_TYPE_RP: /* 0x4 */
printf("Root Port of PCI Express Root Complex\n");
check_slot = true;
break;
@@ -1800,10 +1836,10 @@
/* Upstream port is not PCIe */
check_slot = true;
break;
- case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */
+ case PCIE_XCAP_TYPE_RCIEP: /* 0x9 */
printf("Root Complex Integrated Endpoint\n");
break;
- case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */
+ case PCIE_XCAP_TYPE_RC_EVNTC: /* 0xa */
printf("Root Complex Event Collector\n");
break;
default:
@@ -1869,6 +1905,9 @@
onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP);
printf(" Max Read Request Size: %d byte\n",
128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ));
+ if (pcie_devtype == PCIE_XCAP_TYPE_PCIE2PCI)
+ onoff("Bridge Config Retry Enable", reg,
+ PCIE_DCSR_BRDG_CFG_RETRY);
/* Device Status Register */
reg = regs[o2i(capoff + PCIE_DCSR)];
@@ -2162,6 +2201,8 @@
printf("Reserved\n");
break;
}
+ onoff("10-bit Tag Completer Supported", reg, PCIE_DCAP2_TBT_COMP);
+ onoff("10-bit Tag Requester Supported", reg, PCIE_DCAP2_TBT_REQ);
printf(" OBFF Supported: ");
switch (__SHIFTOUT(reg, PCIE_DCAP2_OBFF)) {
case 0x0:
@@ -2214,6 +2255,7 @@
onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC);
onoff("Emergency Power Reduction Request", reg,
PCIE_DCSR2_EMGPWRRED_REQ);
+ onoff("10-bit Tag Requester Enabled", reg, PCIE_DCSR2_TBT_REQ);
printf(" OBFF: ");
switch (__SHIFTOUT(reg, PCIE_DCSR2_OBFF_EN)) {
case 0x0:
@@ -2254,6 +2296,8 @@
pci_print_pcie_linkspeedvector(
__SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV));
printf("\n");
+ onoff("Retimer Presence Detect Supported", reg,
+ PCIE_LCAP2_RETIMERPD);
onoff("DRS Supported", reg, PCIE_LCAP2_DRS);
drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false;
}
@@ -2273,7 +2317,7 @@
__SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP));
printf("\n");
printf(" Transmit Margin: %u\n",
- (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7);
+ (unsigned int)__SHIFTOUT(reg, PCIE_LCSR2_TX_MARGIN));
onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP);
onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS);
printf(" Compliance Present/De-emphasis: ");
@@ -2558,9 +2602,7 @@
printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64
"\n", base, base + offset);
- entoff += 4;
- entoff += baseis64 ? 8 : 4;
- entoff += offsetis64 ? 8 : 4;
+ entoff += 4 + (4 * entry_size);
}
}
@@ -2675,7 +2717,7 @@
/*
* The type was found. Search capability list again and
- * print all capabilities that the capabiliy type is
+ * print all capabilities that the capability type is
* the same. This is required because some capabilities
* appear multiple times (e.g. HyperTransport capability).
*/
@@ -2842,8 +2884,8 @@
extcapoff + PCI_AER_ROOTERR_CMD);
switch (pcie_devtype) {
- case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */
- case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */
+ case PCIE_XCAP_TYPE_RP: /* Root Port of PCI Express Root Complex */
+ case PCIE_XCAP_TYPE_RC_EVNTC: /* Root Complex Event Collector */
reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)];
printf(" Root Error Command register: 0x%08x\n", reg);
pci_conf_print_aer_cap_rooterr_cmd(reg);
@@ -2864,36 +2906,42 @@
}
}
+/*
+ * Helper function to print the arbitration phase register.
+ *
+ * phases: Number of phases in the arbitration tables.
+ * arbsize: Number of bits in each phase.
+ * indent: Add more two spaces if it's true.
+ */
static void
pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name,
- pcireg_t parbsel, int parbsize)
+ const int phases, int arbsize, bool indent)
{
pcireg_t reg;
- int num = 16 << parbsel;
- int num_per_reg = sizeof(pcireg_t) / parbsize;
+ int num_per_reg = 32 / arbsize;
int i, j;
- /* First, dump the table */
- for (i = 0; i < num; i += num_per_reg) {
- reg = regs[o2i(off + i / num_per_reg)];
- printf(" %s Arbitration Table: 0x%08x\n", name, reg);
- }
- /* And then, decode each entry */
- for (i = 0; i < num; i += num_per_reg) {
- reg = regs[o2i(off + i / num_per_reg)];
- for (j = 0; j < num_per_reg; j++)
- printf(" Phase[%d]: %d\n", j, reg);
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