Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys/dev/pci Use __BIT() some more. Same code before and after.
details: https://anonhg.NetBSD.org/src/rev/937805ad88c2
branches: trunk
changeset: 1029119:937805ad88c2
user: skrll <skrll%NetBSD.org@localhost>
date: Wed Dec 22 07:16:44 2021 +0000
description:
Use __BIT() some more. Same code before and after.
diffstat:
sys/dev/pci/if_wmreg.h | 374 ++++++++++++++++++++++++------------------------
1 files changed, 189 insertions(+), 185 deletions(-)
diffs (truncated from 603 to 300 lines):
diff -r fe4ecdfc23a9 -r 937805ad88c2 sys/dev/pci/if_wmreg.h
--- a/sys/dev/pci/if_wmreg.h Wed Dec 22 02:32:53 2021 +0000
+++ b/sys/dev/pci/if_wmreg.h Wed Dec 22 07:16:44 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wmreg.h,v 1.122 2021/12/20 12:50:35 skrll Exp $ */
+/* $NetBSD: if_wmreg.h,v 1.123 2021/12/22 07:16:44 skrll Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -101,28 +101,28 @@
} __packed wiseman_rxdesc_t;
/* wrx_status bits */
-#define WRX_ST_DD (1U << 0) /* descriptor done */
-#define WRX_ST_EOP (1U << 1) /* end of packet */
-#define WRX_ST_IXSM (1U << 2) /* ignore checksum indication */
-#define WRX_ST_VP (1U << 3) /* VLAN packet */
-#define WRX_ST_BPDU (1U << 4) /* ??? */
-#define WRX_ST_TCPCS (1U << 5) /* TCP checksum performed */
-#define WRX_ST_IPCS (1U << 6) /* IP checksum performed */
-#define WRX_ST_PIF (1U << 7) /* passed in-exact filter */
+#define WRX_ST_DD __BIT(0) /* descriptor done */
+#define WRX_ST_EOP __BIT(1) /* end of packet */
+#define WRX_ST_IXSM __BIT(2) /* ignore checksum indication */
+#define WRX_ST_VP __BIT(3) /* VLAN packet */
+#define WRX_ST_BPDU __BIT(4) /* ??? */
+#define WRX_ST_TCPCS __BIT(5) /* TCP checksum performed */
+#define WRX_ST_IPCS __BIT(6) /* IP checksum performed */
+#define WRX_ST_PIF __BIT(7) /* passed in-exact filter */
/* wrx_error bits */
-#define WRX_ER_CE (1U << 0) /* CRC error */
-#define WRX_ER_SE (1U << 1) /* symbol error */
-#define WRX_ER_SEQ (1U << 2) /* sequence error */
-#define WRX_ER_ICE (1U << 3) /* ??? */
-#define WRX_ER_CXE (1U << 4) /* carrier extension error */
-#define WRX_ER_TCPE (1U << 5) /* TCP checksum error */
-#define WRX_ER_IPE (1U << 6) /* IP checksum error */
-#define WRX_ER_RXE (1U << 7) /* Rx data error */
+#define WRX_ER_CE __BIT(0) /* CRC error */
+#define WRX_ER_SE __BIT(1) /* symbol error */
+#define WRX_ER_SEQ __BIT(2) /* sequence error */
+#define WRX_ER_ICE __BIT(3) /* ??? */
+#define WRX_ER_CXE __BIT(4) /* carrier extension error */
+#define WRX_ER_TCPE __BIT(5) /* TCP checksum error */
+#define WRX_ER_IPE __BIT(6) /* IP checksum error */
+#define WRX_ER_RXE __BIT(7) /* Rx data error */
/* wrx_special field for VLAN packets */
#define WRX_VLAN_ID(x) ((x) & 0x0fff) /* VLAN identifier */
-#define WRX_VLAN_CFI (1U << 12) /* Canonical Form Indicator */
+#define WRX_VLAN_CFI __BIT(12) /* Canonical Form Indicator */
#define WRX_VLAN_PRI(x) (((x) >> 13) & 7)/* VLAN priority field */
/* extended RX descriptor for 82574 */
@@ -348,27 +348,28 @@
} __packed wiseman_txdesc_t;
/* Commands for wtx_cmdlen */
-#define WTX_CMD_EOP (1U << 24) /* end of packet */
-#define WTX_CMD_IFCS (1U << 25) /* insert FCS */
-#define WTX_CMD_RS (1U << 27) /* report status */
-#define WTX_CMD_RPS (1U << 28) /* report packet sent */
-#define WTX_CMD_DEXT (1U << 29) /* descriptor extension */
-#define WTX_CMD_VLE (1U << 30) /* VLAN enable */
-#define WTX_CMD_IDE (1U << 31) /* interrupt delay enable */
+#define WTX_CMD_EOP __BIT(24) /* end of packet */
+#define WTX_CMD_IFCS __BIT(25) /* insert FCS */
+#define WTX_CMD_RS __BIT(27) /* report status */
+#define WTX_CMD_RPS __BIT(28) /* report packet sent */
+#define WTX_CMD_DEXT __BIT(29) /* descriptor extension */
+#define WTX_CMD_VLE __BIT(30) /* VLAN enable */
+#define WTX_CMD_IDE __BIT(31) /* interrupt delay enable */
/* Descriptor types (if DEXT is set) */
-#define WTX_DTYP_C (0U << 20) /* context */
-#define WTX_DTYP_D (1U << 20) /* data */
+#define WTX_DTYP_MASK __BIT(20)
+#define WTX_DTYP_C __SHIFTIN(0, WTX_DTYP_MASK) /* context */
+#define WTX_DTYP_D __SHIFTIN(1, WTX_DTYP_MASK) /* data */
/* wtx_fields status bits */
-#define WTX_ST_DD (1U << 0) /* descriptor done */
-#define WTX_ST_EC (1U << 1) /* excessive collisions */
-#define WTX_ST_LC (1U << 2) /* late collision */
-#define WTX_ST_TU (1U << 3) /* transmit underrun */
+#define WTX_ST_DD __BIT(0) /* descriptor done */
+#define WTX_ST_EC __BIT(1) /* excessive collisions */
+#define WTX_ST_LC __BIT(2) /* late collision */
+#define WTX_ST_TU __BIT(3) /* transmit underrun */
/* wtx_fields option bits for IP/TCP/UDP checksum offload */
-#define WTX_IXSM (1U << 0) /* IP checksum offload */
-#define WTX_TXSM (1U << 1) /* TCP/UDP checksum offload */
+#define WTX_IXSM __BIT(0) /* IP checksum offload */
+#define WTX_TXSM __BIT(1) /* TCP/UDP checksum offload */
/* Maximum payload per Tx descriptor */
#define WTX_MAX_LEN 4096
@@ -384,9 +385,9 @@
};
/* commands for context descriptors */
-#define WTX_TCPIP_CMD_TCP (1U << 24) /* 1 = TCP, 0 = UDP */
-#define WTX_TCPIP_CMD_IP (1U << 25) /* 1 = IPv4, 0 = IPv6 */
-#define WTX_TCPIP_CMD_TSE (1U << 26) /* segmentation context valid */
+#define WTX_TCPIP_CMD_TCP __BIT(24) /* 1 = TCP, 0 = UDP */
+#define WTX_TCPIP_CMD_IP __BIT(25) /* 1 = IPv4, 0 = IPv6 */
+#define WTX_TCPIP_CMD_TSE __BIT(26) /* segmentation context valid */
#define WTX_TCPIP_IPCSS(x) ((x) << 0) /* checksum start */
#define WTX_TCPIP_IPCSO(x) ((x) << 8) /* checksum value offset */
@@ -417,71 +418,71 @@
* Wiseman Control/Status Registers.
*/
#define WMREG_CTRL 0x0000 /* Device Control Register */
-#define CTRL_FD (1U << 0) /* full duplex */
-#define CTRL_BEM (1U << 1) /* big-endian mode */
-#define CTRL_PRIOR (1U << 2) /* 0 = receive, 1 = fair */
-#define CTRL_GIO_M_DIS (1U << 2) /* disabl PCI master access */
-#define CTRL_LRST (1U << 3) /* link reset */
-#define CTRL_ASDE (1U << 5) /* auto speed detect enable */
-#define CTRL_SLU (1U << 6) /* set link up */
-#define CTRL_ILOS (1U << 7) /* invert loss of signal */
+#define CTRL_FD __BIT(0) /* full duplex */
+#define CTRL_BEM __BIT(1) /* big-endian mode */
+#define CTRL_PRIOR __BIT(2) /* 0 = receive, 1 = fair */
+#define CTRL_GIO_M_DIS __BIT(2) /* disabl PCI master access */
+#define CTRL_LRST __BIT(3) /* link reset */
+#define CTRL_ASDE __BIT(5) /* auto speed detect enable */
+#define CTRL_SLU __BIT(6) /* set link up */
+#define CTRL_ILOS __BIT(7) /* invert loss of signal */
#define CTRL_SPEED(x) ((x) << 8) /* speed (Livengood) */
#define CTRL_SPEED_10 CTRL_SPEED(0)
#define CTRL_SPEED_100 CTRL_SPEED(1)
#define CTRL_SPEED_1000 CTRL_SPEED(2)
#define CTRL_SPEED_MASK CTRL_SPEED(3)
-#define CTRL_FRCSPD (1U << 11) /* force speed (Livengood) */
-#define CTRL_FRCFDX (1U << 12) /* force full-duplex (Livengood) */
-#define CTRL_D_UD_EN (1U << 13) /* Dock/Undock enable */
-#define CTRL_D_UD_POL (1U << 14) /* Defined polarity of Dock/Undock indication in SDP[0] */
-#define CTRL_F_PHY_R (1U << 15) /* Reset both PHY ports, through PHYRST_N pin */
-#define CTRL_EXTLINK_EN (1U << 16) /* enable link status from external LINK_0 and LINK_1 pins */
-#define CTRL_LANPHYPC_OVERRIDE (1U << 16) /* SW control of LANPHYPC */
-#define CTRL_LANPHYPC_VALUE (1U << 17) /* SW value of LANPHYPC */
+#define CTRL_FRCSPD __BIT(11) /* force speed (Livengood) */
+#define CTRL_FRCFDX __BIT(12) /* force full-duplex (Livengood) */
+#define CTRL_D_UD_EN __BIT(13) /* Dock/Undock enable */
+#define CTRL_D_UD_POL __BIT(14) /* Defined polarity of Dock/Undock indication in SDP[0] */
+#define CTRL_F_PHY_R __BIT(15) /* Reset both PHY ports, through PHYRST_N pin */
+#define CTRL_EXTLINK_EN __BIT(16) /* enable link status from external LINK_0 and LINK_1 pins */
+#define CTRL_LANPHYPC_OVERRIDE __BIT(16) /* SW control of LANPHYPC */
+#define CTRL_LANPHYPC_VALUE __BIT(17) /* SW value of LANPHYPC */
#define CTRL_SWDPINS_SHIFT 18
#define CTRL_SWDPINS_MASK 0x0f
#define CTRL_SWDPIN(x) (1U << (CTRL_SWDPINS_SHIFT + (x)))
#define CTRL_SWDPIO_SHIFT 22
#define CTRL_SWDPIO_MASK 0x0f
#define CTRL_SWDPIO(x) (1U << (CTRL_SWDPIO_SHIFT + (x)))
-#define CTRL_MEHE (1U << 19) /* Memory Error Handling Enable(I217)*/
-#define CTRL_RST (1U << 26) /* device reset */
-#define CTRL_RFCE (1U << 27) /* Rx flow control enable */
-#define CTRL_TFCE (1U << 28) /* Tx flow control enable */
-#define CTRL_VME (1U << 30) /* VLAN Mode Enable */
-#define CTRL_PHY_RESET (1U << 31) /* PHY reset (Cordova) */
+#define CTRL_MEHE __BIT(19) /* Memory Error Handling Enable(I217)*/
+#define CTRL_RST __BIT(26) /* device reset */
+#define CTRL_RFCE __BIT(27) /* Rx flow control enable */
+#define CTRL_TFCE __BIT(28) /* Tx flow control enable */
+#define CTRL_VME __BIT(30) /* VLAN Mode Enable */
+#define CTRL_PHY_RESET __BIT(31) /* PHY reset (Cordova) */
#define WMREG_CTRL_SHADOW 0x0004 /* Device Control Register (shadow) */
#define WMREG_STATUS 0x0008 /* Device Status Register */
-#define STATUS_FD (1U << 0) /* full duplex */
-#define STATUS_LU (1U << 1) /* link up */
-#define STATUS_TCKOK (1U << 2) /* Tx clock running */
-#define STATUS_RBCOK (1U << 3) /* Rx clock running */
+#define STATUS_FD __BIT(0) /* full duplex */
+#define STATUS_LU __BIT(1) /* link up */
+#define STATUS_TCKOK __BIT(2) /* Tx clock running */
+#define STATUS_RBCOK __BIT(3) /* Rx clock running */
#define STATUS_FUNCID_SHIFT 2 /* 82546 function ID */
#define STATUS_FUNCID_MASK 3 /* ... */
-#define STATUS_TXOFF (1U << 4) /* Tx paused */
-#define STATUS_TBIMODE (1U << 5) /* fiber mode (Livengood) */
+#define STATUS_TXOFF __BIT(4) /* Tx paused */
+#define STATUS_TBIMODE __BIT(5) /* fiber mode (Livengood) */
#define STATUS_SPEED __BITS(7, 6) /* speed indication */
#define STATUS_SPEED_10 0
#define STATUS_SPEED_100 1
#define STATUS_SPEED_1000 2
#define STATUS_ASDV(x) ((x) << 8) /* auto speed det. val. (Livengood) */
-#define STATUS_LAN_INIT_DONE (1U << 9) /* Lan Init Completion by NVM */
-#define STATUS_MTXCKOK (1U << 10) /* MTXD clock running */
-#define STATUS_PHYRA (1U << 10) /* PHY Reset Asserted (PCH) */
-#define STATUS_PCI66 (1U << 11) /* 66MHz bus (Livengood) */
-#define STATUS_BUS64 (1U << 12) /* 64-bit bus (Livengood) */
+#define STATUS_LAN_INIT_DONE __BIT(9) /* Lan Init Completion by NVM */
+#define STATUS_MTXCKOK __BIT(10) /* MTXD clock running */
+#define STATUS_PHYRA __BIT(10) /* PHY Reset Asserted (PCH) */
+#define STATUS_PCI66 __BIT(11) /* 66MHz bus (Livengood) */
+#define STATUS_BUS64 __BIT(12) /* 64-bit bus (Livengood) */
#define STATUS_2P5_SKU __BIT(12) /* Value of the 2.5GBE SKU strap */
-#define STATUS_PCIX_MODE (1U << 13) /* PCIX mode (Cordova) */
+#define STATUS_PCIX_MODE __BIT(13) /* PCIX mode (Cordova) */
#define STATUS_2P5_SKU_OVER __BIT(13) /* Value of the 2.5GBE SKU override */
#define STATUS_PCIXSPD(x) ((x) << 14) /* PCIX speed indication (Cordova) */
#define STATUS_PCIXSPD_50_66 STATUS_PCIXSPD(0)
#define STATUS_PCIXSPD_66_100 STATUS_PCIXSPD(1)
#define STATUS_PCIXSPD_100_133 STATUS_PCIXSPD(2)
#define STATUS_PCIXSPD_MASK STATUS_PCIXSPD(3)
-#define STATUS_GIO_M_ENA (1U << 19) /* GIO master enable */
-#define STATUS_DEV_RST_SET (1U << 20) /* Device Reset Set */
+#define STATUS_GIO_M_ENA __BIT(19) /* GIO master enable */
+#define STATUS_DEV_RST_SET __BIT(20) /* Device Reset Set */
/* Strapping Option Register (PCH_SPT and newer) */
#define WMREG_STRAP 0x000c
@@ -490,25 +491,25 @@
#define STRAP_SMBUSADDR __BITS(17, 23)
#define WMREG_EECD 0x0010 /* EEPROM Control Register */
-#define EECD_SK (1U << 0) /* clock */
-#define EECD_CS (1U << 1) /* chip select */
-#define EECD_DI (1U << 2) /* data in */
-#define EECD_DO (1U << 3) /* data out */
+#define EECD_SK __BIT(0) /* clock */
+#define EECD_CS __BIT(1) /* chip select */
+#define EECD_DI __BIT(2) /* data in */
+#define EECD_DO __BIT(3) /* data out */
#define EECD_FWE(x) ((x) << 4) /* flash write enable control */
#define EECD_FWE_DISABLED EECD_FWE(1)
#define EECD_FWE_ENABLED EECD_FWE(2)
-#define EECD_EE_REQ (1U << 6) /* (shared) EEPROM request */
-#define EECD_EE_GNT (1U << 7) /* (shared) EEPROM grant */
-#define EECD_EE_PRES (1U << 8) /* EEPROM present */
-#define EECD_EE_SIZE (1U << 9) /* EEPROM size
+#define EECD_EE_REQ __BIT(6) /* (shared) EEPROM request */
+#define EECD_EE_GNT __BIT(7) /* (shared) EEPROM grant */
+#define EECD_EE_PRES __BIT(8) /* EEPROM present */
+#define EECD_EE_SIZE __BIT(9) /* EEPROM size
(0 = 64 word, 1 = 256 word) */
-#define EECD_EE_AUTORD (1U << 9) /* auto read done */
-#define EECD_EE_ABITS (1U << 10) /* EEPROM address bits
+#define EECD_EE_AUTORD __BIT(9) /* auto read done */
+#define EECD_EE_ABITS __BIT(10) /* EEPROM address bits
(based on type) */
#define EECD_EE_SIZE_EX_MASK __BITS(14,11) /* EEPROM size for new devices */
-#define EECD_EE_TYPE (1U << 13) /* EEPROM type
+#define EECD_EE_TYPE __BIT(13) /* EEPROM type
(0 = Microwire, 1 = SPI) */
-#define EECD_SEC1VAL (1U << 22) /* Sector One Valid */
+#define EECD_SEC1VAL __BIT(22) /* Sector One Valid */
#define EECD_SEC1VAL_VALMASK (EECD_EE_AUTORD | EECD_EE_PRES) /* Valid Mask */
#define WMREG_FEXTNVM6 0x0010 /* Future Extended NVM 6 */
@@ -537,14 +538,14 @@
#define CTRL_EXT_SWDPIO(x) (1U << (CTRL_EXT_SWDPIO_SHIFT \
+ ((x) == 3 ? 3 : ((x) - 4))))
#define CTRL_EXT_FORCE_SMBUS __BIT(11) /* Force SMBus mode */
-#define CTRL_EXT_ASDCHK (1U << 12) /* ASD check */
-#define CTRL_EXT_EE_RST (1U << 13) /* EEPROM reset */
-#define CTRL_EXT_IPS (1U << 14) /* invert power state bit 0 */
-#define CTRL_EXT_SPD_BYPS (1U << 15) /* speed select bypass */
-#define CTRL_EXT_IPS1 (1U << 16) /* invert power state bit 1 */
-#define CTRL_EXT_RO_DIS (1U << 17) /* relaxed ordering disabled */
-#define CTRL_EXT_SDLPE (1U << 18) /* SerDes Low Power Enable */
-#define CTRL_EXT_DMA_DYN_CLK (1U << 19) /* DMA Dynamic Gating Enable */
+#define CTRL_EXT_ASDCHK __BIT(12) /* ASD check */
+#define CTRL_EXT_EE_RST __BIT(13) /* EEPROM reset */
+#define CTRL_EXT_IPS __BIT(14) /* invert power state bit 0 */
+#define CTRL_EXT_SPD_BYPS __BIT(15) /* speed select bypass */
+#define CTRL_EXT_IPS1 __BIT(16) /* invert power state bit 1 */
+#define CTRL_EXT_RO_DIS __BIT(17) /* relaxed ordering disabled */
+#define CTRL_EXT_SDLPE __BIT(18) /* SerDes Low Power Enable */
+#define CTRL_EXT_DMA_DYN_CLK __BIT(19) /* DMA Dynamic Gating Enable */
#define CTRL_EXT_PHYPDEN __BIT(20)
#define CTRL_EXT_LINK_MODE_MASK 0x00c00000
#define CTRL_EXT_LINK_MODE_GMII 0x00000000
@@ -565,19 +566,21 @@
#define MDIC_PHY_SHIFT 21
#define MDIC_PHY_MASK __BITS(25, 21)
#define MDIC_PHYADD(x) ((x) << 21)
-#define MDIC_OP_WRITE (1U << 26)
-#define MDIC_OP_READ (2U << 26)
-#define MDIC_READY (1U << 28)
-#define MDIC_I (1U << 29) /* interrupt on MDI complete */
-#define MDIC_E (1U << 30) /* MDI error */
-#define MDIC_DEST (1U << 31) /* Destination */
+
+#define MDIC_OP_RW_MASK __BITS(27, 26)
+#define MDIC_OP_WRITE __SHIFTIN(1, MDIC_OP_RW_MASK)
+#define MDIC_OP_READ __SHIFTIN(2, MDIC_OP_RW_MASK)
+#define MDIC_READY __BIT(28)
+#define MDIC_I __BIT(29) /* interrupt on MDI complete */
+#define MDIC_E __BIT(30) /* MDI error */
+#define MDIC_DEST __BIT(31) /* Destination */
Home |
Main Index |
Thread Index |
Old Index