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[src/netbsd-8]: src/sys/arch/x86/include Pull up the following revisions (all...



details:   https://anonhg.NetBSD.org/src/rev/e01fbe7f406e
branches:  netbsd-8
changeset: 359930:e01fbe7f406e
user:      martin <martin%NetBSD.org@localhost>
date:      Mon Jan 31 17:46:36 2022 +0000

description:
Pull up the following revisions (all via patch), requested by
msaitoh in ticket #1731:

        sys/arch/x86/include/specialreg.h               1.179-1.188

- Add CPUID definitions of Last Branch Record, Thread Director,
  AVX version of VNNI, Fast short REP MOV, HRESET, PPIN, Architectural
  LBR, Linear Address Masking and Hybrid Information from the latest
  Intel SDM.
- Add CPUID definitions of AddrMaskExt, INT_WBINVD, IbrsSameMode,
  EferLmsleUnsupported, PSFD and SecureTSC from AMD APM.
- Print CLFSH instead of CLFLUSH because both Intel and AMD documents
  say so.
- Modify comment. Add comment. Fix typo. Use __BIT(). KNF. Sort lines.
  No functional change.

diffstat:

 sys/arch/x86/include/specialreg.h |  635 ++++++++++++++++++++-----------------
 1 files changed, 347 insertions(+), 288 deletions(-)

diffs (truncated from 967 to 300 lines):

diff -r 2051111d4156 -r e01fbe7f406e sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Mon Jan 31 17:38:36 2022 +0000
+++ b/sys/arch/x86/include/specialreg.h Mon Jan 31 17:46:36 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: specialreg.h,v 1.98.2.22 2021/12/08 15:56:17 martin Exp $      */
+/*     $NetBSD: specialreg.h,v 1.98.2.23 2022/01/31 17:46:36 martin Exp $      */
 
 /*
  * Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
@@ -90,29 +90,29 @@
 /*
  * CR4
  */
-#define CR4_VME                0x00000001 /* virtual 8086 mode extension enable */
-#define CR4_PVI                0x00000002 /* protected mode virtual interrupt enable */
-#define CR4_TSD                0x00000004 /* restrict RDTSC instruction to cpl 0 */
-#define CR4_DE         0x00000008 /* debugging extension */
-#define CR4_PSE                0x00000010 /* large (4MB) page size enable */
-#define CR4_PAE                0x00000020 /* physical address extension enable */
-#define CR4_MCE                0x00000040 /* machine check enable */
-#define CR4_PGE                0x00000080 /* page global enable */
-#define CR4_PCE                0x00000100 /* enable RDPMC instruction for all cpls */
-#define CR4_OSFXSR     0x00000200 /* enable fxsave/fxrestor and SSE */
-#define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
-#define CR4_UMIP       0x00000800 /* user-mode instruction prevention */
+#define CR4_VME                0x00000001 /* Virtual 8086 mode extension enable */
+#define CR4_PVI                0x00000002 /* Protected mode virtual interrupt enable */
+#define CR4_TSD                0x00000004 /* Restrict RDTSC instruction to cpl 0 */
+#define CR4_DE         0x00000008 /* Debugging extension */
+#define CR4_PSE                0x00000010 /* Large (4MB) page size enable */
+#define CR4_PAE                0x00000020 /* Physical address extension enable */
+#define CR4_MCE                0x00000040 /* Machine check enable */
+#define CR4_PGE                0x00000080 /* Page global enable */
+#define CR4_PCE                0x00000100 /* Enable RDPMC instruction for all cpls */
+#define CR4_OSFXSR     0x00000200 /* Enable fxsave/fxrestor and SSE */
+#define CR4_OSXMMEXCPT 0x00000400 /* Enable unmasked SSE exceptions */
+#define CR4_UMIP       0x00000800 /* User Mode Instruction Prevention */
 #define CR4_LA57       0x00001000 /* 57-bit linear addresses */
-#define CR4_VMXE       0x00002000 /* enable VMX operations */
-#define CR4_SMXE       0x00004000 /* enable SMX operations */
-#define CR4_FSGSBASE   0x00010000 /* enable *FSBASE and *GSBASE instructions */
-#define CR4_PCIDE      0x00020000 /* enable Process Context IDentifiers */
-#define CR4_OSXSAVE    0x00040000 /* enable xsave and xrestore */
-#define CR4_SMEP       0x00100000 /* enable SMEP support */
-#define CR4_SMAP       0x00200000 /* enable SMAP support */
-#define CR4_PKE                0x00400000 /* enable Protection Keys for user pages */
-#define CR4_CET                0x00800000 /* enable CET */
-#define CR4_PKS                0x01000000 /* enable Protection Keys for kern pages */
+#define CR4_VMXE       0x00002000 /* Enable VMX operations */
+#define CR4_SMXE       0x00004000 /* Enable SMX operations */
+#define CR4_FSGSBASE   0x00010000 /* Enable *FSBASE and *GSBASE instructions */
+#define CR4_PCIDE      0x00020000 /* Enable Process Context IDentifiers */
+#define CR4_OSXSAVE    0x00040000 /* Enable xsave and xrestore */
+#define CR4_SMEP       0x00100000 /* Enable SMEP support */
+#define CR4_SMAP       0x00200000 /* Enable SMAP support */
+#define CR4_PKE                0x00400000 /* Enable Protection Keys for user pages */
+#define CR4_CET                0x00800000 /* Enable CET */
+#define CR4_PKS                0x01000000 /* Enable Protection Keys for kern pages */
 
 /*
  * Extended Control Register XCR0
@@ -130,14 +130,15 @@
 #define XCR0_CET_U     0x00000800      /* User CET state */
 #define XCR0_CET_S     0x00001000      /* Kern CET state */
 #define XCR0_HDC       0x00002000      /* Hardware Duty Cycle state */
+#define XCR0_LBR       0x00008000      /* Last Branch Record */
 #define XCR0_HWP       0x00010000      /* Hardware P-states */
 
-#define XCR0_FLAGS1    "\20" \
-       "\1" "x87"              "\2" "SSE"              "\3" "AVX"      \
-       "\4" "BNDREGS"          "\5" "BNDCSR"           "\6" "Opmask"   \
-       "\7" "ZMM_Hi256"        "\10" "Hi16_ZMM"        "\11" "PT"      \
-       "\12" "PKRU"            "\14" "CET_U"           "\15" "CET_S"   \
-       "\16" "HDC"             "\21" "HWP"
+#define XCR0_FLAGS1    "\20"                                             \
+       "\1" "x87"      "\2" "SSE"      "\3" "AVX"      "\4" "BNDREGS"    \
+       "\5" "BNDCSR"   "\6" "Opmask"   "\7" "ZMM_Hi256" "\10" "Hi16_ZMM" \
+       "\11" "PT"      "\12" "PKRU"                    "\14" "CET_U"     \
+       "\15" "CET_S"   "\16" "HDC"                     "\20" "LBR"       \
+       "\21" "HWP"
 
 /*
  * Known FPU bits, only these get enabled. The save area is sized for all the
@@ -147,17 +148,17 @@
                         XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM)
 
 /*
- * CPUID "features" bits
+ * "features" bits.
+ * CPUID Fn00000001
  */
-
-/* Fn00000001 %edx features */
+/* %edx */
 #define CPUID_FPU      0x00000001      /* processor has an FPU? */
 #define CPUID_VME      0x00000002      /* has virtual mode (%cr4's VME/PVI) */
 #define CPUID_DE       0x00000004      /* has debugging extension */
 #define CPUID_PSE      0x00000008      /* has 4MB page size extension */
 #define CPUID_TSC      0x00000010      /* has time stamp counter */
 #define CPUID_MSR      0x00000020      /* has model specific registers */
-#define CPUID_PAE      0x00000040      /* has phys address extension */
+#define CPUID_PAE      0x00000040      /* has physical address extension */
 #define CPUID_MCE      0x00000080      /* has machine check exception */
 #define CPUID_CX8      0x00000100      /* has CMPXCHG8B instruction */
 #define CPUID_APIC     0x00000200      /* has enabled APIC */
@@ -168,27 +169,27 @@
 #define CPUID_CMOV     0x00008000      /* has CMOVcc instruction */
 #define CPUID_PAT      0x00010000      /* Page Attribute Table */
 #define CPUID_PSE36    0x00020000      /* 36-bit PSE */
-#define CPUID_PSN      0x00040000      /* processor serial number */
-#define CPUID_CLFSH    0x00080000      /* CLFLUSH insn supported */
+#define CPUID_PSN      0x00040000      /* Processor Serial Number */
+#define CPUID_CLFSH    0x00080000      /* CLFLUSH instruction supported */
 #define CPUID_DS       0x00200000      /* Debug Store */
 #define CPUID_ACPI     0x00400000      /* ACPI performance modulation regs */
 #define CPUID_MMX      0x00800000      /* MMX supported */
-#define CPUID_FXSR     0x01000000      /* fast FP/MMX save/restore */
-#define CPUID_SSE      0x02000000      /* streaming SIMD extensions */
-#define CPUID_SSE2     0x04000000      /* streaming SIMD extensions #2 */
-#define CPUID_SS       0x08000000      /* self-snoop */
+#define CPUID_FXSR     0x01000000      /* Fast FP/MMX Save/Restore */
+#define CPUID_SSE      0x02000000      /* Streaming SIMD Extensions */
+#define CPUID_SSE2     0x04000000      /* Streaming SIMD Extensions #2 */
+#define CPUID_SS       0x08000000      /* Self-Snoop */
 #define CPUID_HTT      0x10000000      /* Hyper-Threading Technology */
-#define CPUID_TM       0x20000000      /* thermal monitor (TCC) */
+#define CPUID_TM       0x20000000      /* Thermal Monitor (TCC) */
 #define CPUID_PBE      0x80000000      /* Pending Break Enable */
 
-#define CPUID_FLAGS1   "\20" \
-       "\1" "FPU"      "\2" "VME"      "\3" "DE"       "\4" "PSE" \
-       "\5" "TSC"      "\6" "MSR"      "\7" "PAE"      "\10" "MCE" \
-       "\11" "CX8"     "\12" "APIC"    "\13" "B10"     "\14" "SEP" \
-       "\15" "MTRR"    "\16" "PGE"     "\17" "MCA"     "\20" "CMOV" \
-       "\21" "PAT"     "\22" "PSE36"   "\23" "PN"      "\24" "CLFLUSH" \
-       "\25" "B20"     "\26" "DS"      "\27" "ACPI"    "\30" "MMX" \
-       "\31" "FXSR"    "\32" "SSE"     "\33" "SSE2"    "\34" "SS" \
+#define CPUID_FLAGS1   "\20"                                           \
+       "\1" "FPU"      "\2" "VME"      "\3" "DE"       "\4" "PSE"      \
+       "\5" "TSC"      "\6" "MSR"      "\7" "PAE"      "\10" "MCE"     \
+       "\11" "CX8"     "\12" "APIC"    "\13" "B10"     "\14" "SEP"     \
+       "\15" "MTRR"    "\16" "PGE"     "\17" "MCA"     "\20" "CMOV"    \
+       "\21" "PAT"     "\22" "PSE36"   "\23" "PN"      "\24" "CLFSH"   \
+       "\25" "B20"     "\26" "DS"      "\27" "ACPI"    "\30" "MMX"     \
+       "\31" "FXSR"    "\32" "SSE"     "\33" "SSE2"    "\34" "SS"      \
        "\35" "HTT"     "\36" "TM"      "\37" "IA64"    "\40" "PBE"
 
 /* Blacklists of CPUID flags - used to mask certain features */
@@ -198,24 +199,21 @@
 #define CPUID_FEAT_BLACKLIST    0
 #endif
 
-/*
- * CPUID "features" bits in Fn00000001 %ecx
- */
-
+/* %ecx */
 #define CPUID2_SSE3    0x00000001      /* Streaming SIMD Extensions 3 */
 #define CPUID2_PCLMULQDQ 0x00000002    /* PCLMULQDQ instructions */
 #define CPUID2_DTES64  0x00000004      /* 64-bit Debug Trace */
 #define CPUID2_MONITOR 0x00000008      /* MONITOR/MWAIT instructions */
 #define CPUID2_DS_CPL  0x00000010      /* CPL Qualified Debug Store */
-#define CPUID2_VMX     0x00000020      /* Virtual Machine Extensions */
-#define CPUID2_SMX     0x00000040      /* Safer Mode Extensions */
+#define CPUID2_VMX     0x00000020      /* Virtual Machine eXtensions */
+#define CPUID2_SMX     0x00000040      /* Safer Mode eXtensions */
 #define CPUID2_EST     0x00000080      /* Enhanced SpeedStep Technology */
 #define CPUID2_TM2     0x00000100      /* Thermal Monitor 2 */
 #define CPUID2_SSSE3   0x00000200      /* Supplemental SSE3 */
 #define CPUID2_CNXTID  0x00000400      /* Context ID */
 #define CPUID2_SDBG    0x00000800      /* Silicon Debug */
-#define CPUID2_FMA     0x00001000      /* has Fused Multiply Add */
-#define CPUID2_CX16    0x00002000      /* has CMPXCHG16B instruction */
+#define CPUID2_FMA     0x00001000      /* Fused Multiply Add */
+#define CPUID2_CX16    0x00002000      /* CMPXCHG16B instruction */
 #define CPUID2_XTPR    0x00004000      /* Task Priority Messages disabled? */
 #define CPUID2_PDCM    0x00008000      /* Perf/Debug Capability MSR */
 /* bit 16 unused       0x00010000 */
@@ -225,7 +223,7 @@
 #define CPUID2_SSE42   0x00100000      /* Streaming SIMD Extensions 4.2 */
 #define CPUID2_X2APIC  0x00200000      /* xAPIC Extensions */
 #define CPUID2_MOVBE   0x00400000      /* MOVBE (move after byteswap) */
-#define CPUID2_POPCNT  0x00800000      /* popcount instruction available */
+#define CPUID2_POPCNT  0x00800000      /* POPCNT instruction available */
 #define CPUID2_DEADLINE        0x01000000      /* APIC Timer supports TSC Deadline */
 #define CPUID2_AESNI   0x02000000      /* AES instructions */
 #define CPUID2_XSAVE   0x04000000      /* XSAVE instructions */
@@ -235,18 +233,17 @@
 #define CPUID2_RDRAND  0x40000000      /* RDRAND (hardware random number) */
 #define CPUID2_RAZ     0x80000000      /* RAZ. Indicates guest state. */
 
-#define CPUID2_FLAGS1  "\20" \
-       "\1" "SSE3"     "\2" "PCLMULQDQ" "\3" "DTES64"  "\4" "MONITOR" \
-       "\5" "DS-CPL"   "\6" "VMX"      "\7" "SMX"      "\10" "EST" \
-       "\11" "TM2"     "\12" "SSSE3"   "\13" "CID"     "\14" "SDBG" \
-       "\15" "FMA"     "\16" "CX16"    "\17" "xTPR"    "\20" "PDCM" \
-       "\21" "B16"     "\22" "PCID"    "\23" "DCA"     "\24" "SSE41" \
-       "\25" "SSE42"   "\26" "X2APIC"  "\27" "MOVBE"   "\30" "POPCNT" \
-       "\31" "DEADLINE" "\32" "AES"    "\33" "XSAVE"   "\34" "OSXSAVE" \
+#define CPUID2_FLAGS1  "\20"                                           \
+       "\1" "SSE3"     "\2" "PCLMULQDQ" "\3" "DTES64"  "\4" "MONITOR"  \
+       "\5" "DS-CPL"   "\6" "VMX"      "\7" "SMX"      "\10" "EST"     \
+       "\11" "TM2"     "\12" "SSSE3"   "\13" "CID"     "\14" "SDBG"    \
+       "\15" "FMA"     "\16" "CX16"    "\17" "xTPR"    "\20" "PDCM"    \
+       "\21" "B16"     "\22" "PCID"    "\23" "DCA"     "\24" "SSE41"   \
+       "\25" "SSE42"   "\26" "X2APIC"  "\27" "MOVBE"   "\30" "POPCNT"  \
+       "\31" "DEADLINE" "\32" "AES"    "\33" "XSAVE"   "\34" "OSXSAVE" \
        "\35" "AVX"     "\36" "F16C"    "\37" "RDRAND"  "\40" "RAZ"
 
-/* CPUID Fn00000001 %eax */
-
+/* %eax */
 #define CPUID_TO_BASEFAMILY(cpuid)     (((cpuid) >> 8) & 0xf)
 #define CPUID_TO_BASEMODEL(cpuid)      (((cpuid) >> 4) & 0xf)
 #define CPUID_TO_STEPPING(cpuid)       ((cpuid) & 0xf)
@@ -270,15 +267,15 @@
                && (CPUID_TO_BASEFAMILY(cpuid) != 0x06)         \
                ? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4)))
 
-/* CPUID Fn00000001 %ebx */
+/* %ebx */
 #define CPUID_BRAND_INDEX      __BITS(7,0)
 #define CPUID_CLFLUSH_SIZE     __BITS(15,8)
 #define CPUID_HTT_CORES                __BITS(23,16)
 #define CPUID_LOCAL_APIC_ID    __BITS(31,24)
 
 /*
- * Intel Deterministic Cache Parameter Leaf
- * Fn0000_0004
+ * Intel Deterministic Cache Parameter.
+ * CPUID Fn0000_0004
  */
 
 /* %eax */
@@ -298,7 +295,7 @@
 #define CPUID_DCP_PARTITIONS   __BITS(21, 12)  /* Physical line partitions */
 #define CPUID_DCP_WAYS         __BITS(31, 22)  /* Ways of associativity */
 
-/* Number of sets: %ecx */
+/* %ecx: Number of sets */
 
 /* %edx */
 #define CPUID_DCP_INVALIDATE   __BIT(0)        /* WB invalidate/invalidate */
@@ -306,8 +303,8 @@
 #define CPUID_DCP_COMPLEX      __BIT(2)        /* Complex cache indexing */
 
 /*
- * Intel/AMD MONITOR/MWAIT
- * Fn0000_0005
+ * Intel/AMD MONITOR/MWAIT.
+ * CPUID Fn0000_0005
  */
 /* %eax */
 #define CPUID_MON_MINSIZE      __BITS(15, 0)  /* Smallest monitor-line size */
@@ -324,48 +321,51 @@
 #define CPUID_MON_SUBSTATE(edx, cstate) (((edx) >> (cstate * 4)) & 0x0000000f)
 
 /*
- * Intel/AMD Digital Thermal Sensor and
- * Power Management, Fn0000_0006 - %eax.
+ * Intel/AMD Digital Thermal Sensor and Power Management.
+ * CPUID Fn0000_0006
  */
-#define CPUID_DSPM_DTS __BIT(0)        /* Digital Thermal Sensor */
-#define CPUID_DSPM_IDA __BIT(1)        /* Intel Dynamic Acceleration */
-#define CPUID_DSPM_ARAT        __BIT(2)        /* Always Running APIC Timer */
-#define CPUID_DSPM_PLN __BIT(4)        /* Power Limit Notification */
-#define CPUID_DSPM_ECMD        __BIT(5)        /* Clock Modulation Extension */
-#define CPUID_DSPM_PTM __BIT(6)        /* Package Level Thermal Management */
-#define CPUID_DSPM_HWP __BIT(7)        /* HWP */
+/* %eax */
+#define CPUID_DSPM_DTS       __BIT(0)  /* Digital Thermal Sensor */
+#define CPUID_DSPM_IDA       __BIT(1)  /* Intel Dynamic Acceleration */
+#define CPUID_DSPM_ARAT              __BIT(2)  /* Always Running APIC Timer */
+#define CPUID_DSPM_PLN       __BIT(4)  /* Power Limit Notification */
+#define CPUID_DSPM_ECMD              __BIT(5)  /* Clock Modulation Extension */
+#define CPUID_DSPM_PTM       __BIT(6)  /* Package Level Thermal Management */
+#define CPUID_DSPM_HWP       __BIT(7)  /* HWP */
 #define CPUID_DSPM_HWP_NOTIFY __BIT(8) /* HWP Notification */
-#define CPUID_DSPM_HWP_ACTWIN  __BIT(9)        /* HWP Activity Window */
-#define CPUID_DSPM_HWP_EPP __BIT(10)   /* HWP Energy Performance Preference */
-#define CPUID_DSPM_HWP_PLR __BIT(11)   /* HWP Package Level Request */
-#define CPUID_DSPM_HDC __BIT(13)       /* Hardware Duty Cycling */
-#define CPUID_DSPM_TBMT3 __BIT(14)     /* Turbo Boost Max Technology 3.0 */
+#define CPUID_DSPM_HWP_ACTWIN __BIT(9) /* HWP Activity Window */
+#define CPUID_DSPM_HWP_EPP    __BIT(10)        /* HWP Energy Performance Preference */
+#define CPUID_DSPM_HWP_PLR    __BIT(11)        /* HWP Package Level Request */
+#define CPUID_DSPM_HDC       __BIT(13) /* Hardware Duty Cycling */
+#define CPUID_DSPM_TBMT3      __BIT(14)        /* Turbo Boost Max Technology 3.0 */
 #define CPUID_DSPM_HWP_CAP    __BIT(15)        /* HWP Capabilities */
 #define CPUID_DSPM_HWP_PECI   __BIT(16)        /* HWP PECI override */
 #define CPUID_DSPM_HWP_FLEX   __BIT(17)        /* Flexible HWP */
 #define CPUID_DSPM_HWP_FAST   __BIT(18)        /* Fast access for IA32_HWP_REQUEST */
 #define CPUID_DSPM_HW_FEEDBACK __BIT(19) /* HW_FEEDBACK*, IA32_PACKAGE_TERM* */
 #define CPUID_DSPM_HWP_IGNIDL __BIT(20)        /* Ignore Idle Logical Processor HWP */
+#define CPUID_DSPM_TD  __BIT(23)       /* Thread Director */
 
-#define CPUID_DSPM_FLAGS       "\20" \
-       "\1" "DTS"      "\2" "IDA"      "\3" "ARAT"                     \
-       "\5" "PLN"      "\6" "ECMD"     "\7" "PTM"      "\10" "HWP"     \



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