[src/trunk]: src/sys/dev/ic add some register bits for interrupt control/erro...

[mrg <mrg%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/78d1965ba864
branches:  trunk
changeset: 363936:78d1965ba864
user:      mrg <mrg%NetBSD.org@localhost>
date:      Thu Mar 17 05:45:23 2022 +0000

description:
add some register bits for interrupt control/error status.
(not yet used.)

diffstat:

 sys/dev/ic/dwc_eqos_reg.h |  24 +++++++++++++++++++++++-
 1 files changed, 23 insertions(+), 1 deletions(-)

diffs (41 lines):

diff -r 3e1b55562c84 -r 78d1965ba864 sys/dev/ic/dwc_eqos_reg.h
--- a/sys/dev/ic/dwc_eqos_reg.h Wed Mar 16 23:56:55 2022 +0000
+++ b/sys/dev/ic/dwc_eqos_reg.h Thu Mar 17 05:45:23 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: dwc_eqos_reg.h,v 1.3 2022/01/09 00:36:28 mrg Exp $ */
+/* $NetBSD: dwc_eqos_reg.h,v 1.4 2022/03/17 05:45:23 mrg Exp $ */
 
 /*-
  * Copyright (c) 2022 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -118,9 +118,31 @@
 #define        GMAC_MAC_ADDRESS0_HIGH                  0x0300
 #define        GMAC_MAC_ADDRESS0_LOW                   0x0304
 #define        GMAC_MMC_CONTROL                        0x0700
+#define         GMAC_MMC_CONTROL_UCDBC                 (1U << 8)
+#define         GMAC_MMC_CONTROL_CNTPRSTLVL            (1U << 5)
+#define         GMAC_MMC_CONTROL_CNTPRST               (1U << 4)
+#define         GMAC_MMC_CONTROL_CNTFREEZ              (1U << 3)
+#define         GMAC_MMC_CONTROL_RSTONRD               (1U << 2)
+#define         GMAC_MMC_CONTROL_CNTSTOPRO             (1U << 1)
+#define         GMAC_MMC_CONTROL_CNTRST                (1U << 0)
 #define        GMAC_MMC_RX_INTERRUPT                   0x0704
+#define         GMAC_MMC_RX_INTERRUPT_RXFOVPIS         (1U << 21)
+#define         GMAC_MMC_RX_INTERRUPT_RXLENERPIS       (1U << 18)
+#define         GMAC_MMC_RX_INTERRUPT_RXCRCERPIS       (1U << 5)
+#define         GMAC_MMC_RX_INTERRUPT_RXMCGPIS         (1U << 4)
+#define         GMAC_MMC_RX_INTERRUPT_RXGOCTIS         (1U << 2)
+#define         GMAC_MMC_RX_INTERRUPT_RXGBOCTIS        (1U << 1)
+#define         GMAC_MMC_RX_INTERRUPT_RXGBPKTIS        (1U << 0)
 #define        GMAC_MMC_TX_INTERRUPT                   0x0708
+#define         GMAC_MMC_TX_INTERRUPT_TXGPKTIS         (1U << 21)
+#define         GMAC_MMC_TX_INTERRUPT_TXGOCTIS         (1U << 20)
+#define         GMAC_MMC_TX_INTERRUPT_TXCARERPIS       (1U << 19)
+#define         GMAC_MMC_TX_INTERRUPT_TXFLOWERPIS      (1U << 13)
+#define         GMAC_MMC_TX_INTERRUPT_TXGBPKTIS        (1U << 1)
+#define         GMAC_MMC_TX_INTERRUPT_TXGBOCTIS        (1U << 0)
+/* Use GMAC_MMC_RX_INTERRUPT_MASK bits for GMAC_MMC_RX_INTERRUPT_MASK */
 #define        GMAC_MMC_RX_INTERRUPT_MASK              0x070C
+/* Use GMAC_MMC_TX_INTERRUPT_MASK bits for GMAC_MMC_TX_INTERRUPT_MASK */
 #define        GMAC_MMC_TX_INTERRUPT_MASK              0x0710
 #define        GMAC_TX_OCTET_COUNT_GOOD_BAD            0x0714
 #define        GMAC_TX_PACKET_COUNT_GOOD_BAD           0x0718