[src/trunk]: src/sys/arch/mips/cavium mips/cavium: Fix membars around establi...

[riastradh <riastradh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/9e5877068e1c
branches:  trunk
changeset: 364418:9e5877068e1c
user:      riastradh <riastradh%NetBSD.org@localhost>
date:      Wed Mar 23 23:24:21 2022 +0000

description:
mips/cavium: Fix membars around establishing interrupt handlers.

diffstat:

 sys/arch/mips/cavium/octeon_intr.c |  29 ++++++++++++++++++++---------
 1 files changed, 20 insertions(+), 9 deletions(-)

diffs (81 lines):

diff -r 8366a44f68c4 -r 9e5877068e1c sys/arch/mips/cavium/octeon_intr.c
--- a/sys/arch/mips/cavium/octeon_intr.c        Wed Mar 23 23:23:25 2022 +0000
+++ b/sys/arch/mips/cavium/octeon_intr.c        Wed Mar 23 23:24:21 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: octeon_intr.c,v 1.24 2020/08/18 07:41:41 skrll Exp $   */
+/*     $NetBSD: octeon_intr.c,v 1.25 2022/03/23 23:24:21 riastradh Exp $       */
 /*
  * Copyright 2001, 2002 Wasabi Systems, Inc.
  * All rights reserved.
@@ -44,7 +44,7 @@
 #define __INTR_PRIVATE
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.24 2020/08/18 07:41:41 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.25 2022/03/23 23:24:21 riastradh Exp $");
 
 #include <sys/param.h>
 #include <sys/cpu.h>
@@ -54,6 +54,7 @@
 #include <sys/kernel.h>
 #include <sys/kmem.h>
 #include <sys/atomic.h>
+#include <sys/xcall.h>
 
 #include <lib/libkern/libkern.h>
 
@@ -353,6 +354,14 @@
        ih->ih_irq = irq;
        ih->ih_ipl = ipl;
 
+       /*
+        * Make sure the initialization is visible on all CPUs before
+        * we expose it in octciu_intrs.  This way we don't need to
+        * issue any membar for a load-acquire when handling the
+        * interrupt.
+        */
+       xc_barrier(0);
+
        mutex_enter(&octeon_intr_lock);
 
        /*
@@ -361,8 +370,7 @@
        KASSERTMSG(octciu_intrs[irq] == NULL, "irq %d in use! (%p)",
            irq, octciu_intrs[irq]);
 
-       octciu_intrs[irq] = ih;
-       membar_producer();
+       atomic_store_relaxed(&octciu_intrs[irq], ih);
 
        /*
         * Now enable it.
@@ -462,13 +470,15 @@
                break;
        }
 
-       /*
-        * Now remove it since we shouldn't get interrupts for it.
-        */
-       octciu_intrs[irq] = NULL;
+       atomic_store_relaxed(&octciu_intrs[irq], NULL);
 
        mutex_exit(&octeon_intr_lock);
 
+       /*
+        * Wait until the interrupt handler is no longer running on all
+        * CPUs before freeing ih and returning.
+        */
+       xc_barrier(0);
        kmem_free(ih, sizeof(*ih));
 }
 
@@ -507,7 +517,8 @@
                        const int irq = (bank * 64) + bit;
                        hwpend[bank] &= ~__BIT(bit);
 
-                       struct octeon_intrhand * const ih = octciu_intrs[irq];
+                       struct octeon_intrhand * const ih =
+                           atomic_load_relaxed(&octciu_intrs[irq]);
                        cpu->cpu_intr_evs[irq].ev_count++;
                        if (__predict_true(ih != NULL)) {
 #ifdef MULTIPROCESSOR