[src/trunk]: src/sys/arch/mips/cavium mips/cavium: Simplify membars around in...

[riastradh <riastradh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/c7cae06838f5
branches:  trunk
changeset: 364474:c7cae06838f5
user:      riastradh <riastradh%NetBSD.org@localhost>
date:      Sat Mar 26 19:38:00 2022 +0000

description:
mips/cavium: Simplify membars around interrupt establishment.

Previously I used xc_barrier to ensure the initialization of the
struct octeon_intrhand was witnessed on all CPUs before publishing
it, in order to avoid needing any barrier on the usage side to be
issued by the interrupt handler.

But there's no need to avoid atomic_load_consume at time of
interrupt: on MIPS it's the same as atomic_load_relaxed anyway, so
there's no additional memory barrier cost here.

diffstat:

 sys/arch/mips/cavium/octeon_intr.c |  16 ++++------------
 1 files changed, 4 insertions(+), 12 deletions(-)

diffs (51 lines):

diff -r 916b3ddbf130 -r c7cae06838f5 sys/arch/mips/cavium/octeon_intr.c
--- a/sys/arch/mips/cavium/octeon_intr.c        Sat Mar 26 19:35:56 2022 +0000
+++ b/sys/arch/mips/cavium/octeon_intr.c        Sat Mar 26 19:38:00 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: octeon_intr.c,v 1.25 2022/03/23 23:24:21 riastradh Exp $       */
+/*     $NetBSD: octeon_intr.c,v 1.26 2022/03/26 19:38:00 riastradh Exp $       */
 /*
  * Copyright 2001, 2002 Wasabi Systems, Inc.
  * All rights reserved.
@@ -44,7 +44,7 @@
 #define __INTR_PRIVATE
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.25 2022/03/23 23:24:21 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.26 2022/03/26 19:38:00 riastradh Exp $");
 
 #include <sys/param.h>
 #include <sys/cpu.h>
@@ -354,14 +354,6 @@
        ih->ih_irq = irq;
        ih->ih_ipl = ipl;
 
-       /*
-        * Make sure the initialization is visible on all CPUs before
-        * we expose it in octciu_intrs.  This way we don't need to
-        * issue any membar for a load-acquire when handling the
-        * interrupt.
-        */
-       xc_barrier(0);
-
        mutex_enter(&octeon_intr_lock);
 
        /*
@@ -370,7 +362,7 @@
        KASSERTMSG(octciu_intrs[irq] == NULL, "irq %d in use! (%p)",
            irq, octciu_intrs[irq]);
 
-       atomic_store_relaxed(&octciu_intrs[irq], ih);
+       atomic_store_release(&octciu_intrs[irq], ih);
 
        /*
         * Now enable it.
@@ -518,7 +510,7 @@
                        hwpend[bank] &= ~__BIT(bit);
 
                        struct octeon_intrhand * const ih =
-                           atomic_load_relaxed(&octciu_intrs[irq]);
+                           atomic_load_consume(&octciu_intrs[irq]);
                        cpu->cpu_intr_evs[irq].ev_count++;
                        if (__predict_true(ih != NULL)) {
 #ifdef MULTIPROCESSOR