[src/trunk]: src/sys/arch Instead of hard-coding SPR# for CCR0, define SPR_CC...

[rin <rin%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/c5a538409957
branches:  trunk
changeset: 365962:c5a538409957
user:      rin <rin%NetBSD.org@localhost>
date:      Sat May 07 04:12:54 2022 +0000

description:
Instead of hard-coding SPR# for CCR0, define SPR_CCR0 in
<powerpc/spr.h> and use it.

Idea from uwe@, thanks!
(and sorry for delayed response!)

diffstat:

 sys/arch/evbppc/dht/locore.S   |  6 +++---
 sys/arch/powerpc/include/spr.h |  3 ++-
 2 files changed, 5 insertions(+), 4 deletions(-)

diffs (38 lines):

diff -r 72333195e01c -r c5a538409957 sys/arch/evbppc/dht/locore.S
--- a/sys/arch/evbppc/dht/locore.S      Fri May 06 06:09:50 2022 +0000
+++ b/sys/arch/evbppc/dht/locore.S      Sat May 07 04:12:54 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.S,v 1.2 2022/02/20 18:56:01 christos Exp $      */
+/*     $NetBSD: locore.S,v 1.3 2022/05/07 04:12:54 rin Exp $   */
 
 /*
  * Taken from src/sys/arch/powerpc/ibm4xx/openbios/locore.s:
@@ -120,9 +120,9 @@
         * Note:        Meaning of bits we need to set is undocumented.
         */
        sync
-       mfspr   %r0,947         /* mfccr0  %r0 */
+       mfspr   %r0,SPR_CCR0    /* XXXclang: mfccr0 %r0 */
        oris    %r0,%r0,0x50000000@h
-       mtspr   947,%r0         /* mtccr0  %r0 */
+       mtspr   SPR_CCR0,%r0    /* XXXclang: mtccr0 %r0 */
        isync
 
        /* PPC405GP errata, item #58.
diff -r 72333195e01c -r c5a538409957 sys/arch/powerpc/include/spr.h
--- a/sys/arch/powerpc/include/spr.h    Fri May 06 06:09:50 2022 +0000
+++ b/sys/arch/powerpc/include/spr.h    Sat May 07 04:12:54 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: spr.h,v 1.54 2021/11/02 11:21:24 ryo Exp $     */
+/*     $NetBSD: spr.h,v 1.55 2022/05/07 04:12:54 rin Exp $     */
 
 /*
  * Copyright (c) 2001, The NetBSD Foundation, Inc.
@@ -144,6 +144,7 @@
 #define        SPR_TBL                 0x11c   /* E468 Time Base Lower */
 #define        SPR_TBU                 0x11d   /* E468 Time Base Upper */
 #define        SPR_PVR                 0x11f   /* E468 Processor Version Register */
+#define        SPR_CCR0                0x3b3   /* .4.. Core Configuration Register */
 
 /* Time Base Register declarations */
 #define        TBR_TBL                 0x10c   /* E468 Time Base Lower */