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[src/trunk]: src/sys/arch Remove GIC_SPLFUNCS.
details: https://anonhg.NetBSD.org/src/rev/23c279a18e24
branches: trunk
changeset: 368137:23c279a18e24
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Sat Jun 25 13:24:34 2022 +0000
description:
Remove GIC_SPLFUNCS.
diffstat:
sys/arch/aarch64/aarch64/genassym.cf | 5 +--
sys/arch/aarch64/aarch64/vectors.S | 22 +-----------
sys/arch/aarch64/conf/files.aarch64 | 5 +--
sys/arch/aarch64/include/cpu.h | 4 +-
sys/arch/arm/cortex/files.cortex | 5 +--
sys/arch/arm/cortex/gic.c | 12 +------
sys/arch/arm/cortex/gicv3.c | 12 +------
sys/arch/arm/fdt/fdt_intr.h | 6 +---
sys/arch/arm/gemini/gemini_intr.h | 6 +---
sys/arch/arm/imx/imx31_intr.h | 6 +---
sys/arch/arm/imx/imx51_intr.h | 6 +---
sys/arch/arm/marvell/mvsoc_intr.h | 6 +---
sys/arch/arm/omap/omap2_intr.h | 6 +---
sys/arch/arm/pic/pic_splfuncs.c | 59 ++++-------------------------------
sys/arch/arm/pic/picvar.h | 8 ++--
sys/arch/evbarm/conf/std.generic64 | 3 +-
16 files changed, 30 insertions(+), 141 deletions(-)
diffs (truncated from 454 to 300 lines):
diff -r 14a70db30d7d -r 23c279a18e24 sys/arch/aarch64/aarch64/genassym.cf
--- a/sys/arch/aarch64/aarch64/genassym.cf Sat Jun 25 13:20:30 2022 +0000
+++ b/sys/arch/aarch64/aarch64/genassym.cf Sat Jun 25 13:24:34 2022 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.37 2021/10/30 20:23:11 jmcneill Exp $
+# $NetBSD: genassym.cf,v 1.38 2022/06/25 13:24:34 jmcneill Exp $
#-
# Copyright (c) 2014 The NetBSD Foundation, Inc.
# All rights reserved.
@@ -298,9 +298,6 @@
define CI_SOFTINTS offsetof(struct cpu_info, ci_softints)
define CI_IDLELWP offsetof(struct cpu_info, ci_data.cpu_idlelwp)
define CI_CC_NINTR offsetof(struct cpu_info, ci_data.cpu_nintr)
-define CI_SPLX_RESTART offsetof(struct cpu_info, ci_splx_restart)
-define CI_SPLX_SAVEDIPL offsetof(struct cpu_info, ci_splx_savedipl)
-define CI_HWPL offsetof(struct cpu_info, ci_hwpl)
define V_RESCHED_KPREEMPT ilog2(RESCHED_KPREEMPT)
diff -r 14a70db30d7d -r 23c279a18e24 sys/arch/aarch64/aarch64/vectors.S
--- a/sys/arch/aarch64/aarch64/vectors.S Sat Jun 25 13:20:30 2022 +0000
+++ b/sys/arch/aarch64/aarch64/vectors.S Sat Jun 25 13:24:34 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: vectors.S,v 1.27 2022/05/29 23:39:59 ryo Exp $ */
+/* $NetBSD: vectors.S,v 1.28 2022/06/25 13:24:34 jmcneill Exp $ */
#include <aarch64/asm.h>
#include <aarch64/locore.h>
@@ -11,7 +11,7 @@
#include "opt_dtrace.h"
#include "opt_gic.h"
-RCSID("$NetBSD: vectors.S,v 1.27 2022/05/29 23:39:59 ryo Exp $")
+RCSID("$NetBSD: vectors.S,v 1.28 2022/06/25 13:24:34 jmcneill Exp $")
ARMV8_DEFINE_OPTIONS
@@ -227,23 +227,7 @@
unwind_x3_x30
-#ifdef GIC_SPLFUNCS
- mrs x0, tpidr_el1 /* get curlwp */
- ldr x0, [x0, #L_CPU] /* get curcpu */
-
- /*
- * If ci_intr_depth == 0 and ci_splx_restart != 0, return
- * to splx restart. Otherwise return to exception pc.
- */
- ldr w1, [x0, #CI_INTR_DEPTH]
- cbnz w1, 1f
- ldr x0, [x0, #CI_SPLX_RESTART]
- cbnz x0, 2f
-1:
- ldr x0, [sp, #TF_PC]
-2:
- ldr x1, [sp, #TF_SPSR]
-#elif TF_PC + 8 == TF_SPSR
+#if TF_PC + 8 == TF_SPSR
ldp x0, x1, [sp, #TF_PC]
#else
ldr x0, [sp, #TF_PC]
diff -r 14a70db30d7d -r 23c279a18e24 sys/arch/aarch64/conf/files.aarch64
--- a/sys/arch/aarch64/conf/files.aarch64 Sat Jun 25 13:20:30 2022 +0000
+++ b/sys/arch/aarch64/conf/files.aarch64 Sat Jun 25 13:24:34 2022 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.aarch64,v 1.37 2022/01/31 09:16:09 ryo Exp $
+# $NetBSD: files.aarch64,v 1.38 2022/06/25 13:24:34 jmcneill Exp $
defflag opt_cpuoptions.h AARCH64_ALIGNMENT_CHECK
defflag opt_cpuoptions.h AARCH64_EL0_STACK_ALIGNMENT_CHECK
@@ -120,9 +120,6 @@
file uvm/pmap/pmap_tlb.c
file uvm/pmap/pmap_pvt.c
-# GIC
-file arch/arm/cortex/gic_splfuncs_armv8.S gic_splfuncs
-
# EFI runtime (machdep)
file arch/aarch64/aarch64/efi_machdep.c efi_runtime
diff -r 14a70db30d7d -r 23c279a18e24 sys/arch/aarch64/include/cpu.h
--- a/sys/arch/aarch64/include/cpu.h Sat Jun 25 13:20:30 2022 +0000
+++ b/sys/arch/aarch64/include/cpu.h Sat Jun 25 13:24:34 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.46 2022/06/25 12:41:56 jmcneill Exp $ */
+/* $NetBSD: cpu.h,v 1.47 2022/06/25 13:24:34 jmcneill Exp $ */
/*-
* Copyright (c) 2014, 2020 The NetBSD Foundation, Inc.
@@ -134,8 +134,6 @@
volatile uint32_t ci_blocked_pics;
volatile uint32_t ci_pending_pics;
volatile uint32_t ci_pending_ipls;
- void *ci_splx_restart;
- int ci_splx_savedipl;
int ci_kfpu_spl;
diff -r 14a70db30d7d -r 23c279a18e24 sys/arch/arm/cortex/files.cortex
--- a/sys/arch/arm/cortex/files.cortex Sat Jun 25 13:20:30 2022 +0000
+++ b/sys/arch/arm/cortex/files.cortex Sat Jun 25 13:24:34 2022 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.cortex,v 1.16 2021/08/10 17:12:31 jmcneill Exp $
+# $NetBSD: files.cortex,v 1.17 2022/06/25 13:24:34 jmcneill Exp $
defflag opt_cpu_in_cksum.h NEON_IN_CKSUM
@@ -11,9 +11,6 @@
attach armperiph at mainbus
file arch/arm/cortex/armperiph.c armperiph
-defflag opt_gic.h GIC_SPLFUNCS
-file arch/arm/cortex/gic_splfuncs.c gic_splfuncs
-
# ARM Generic Interrupt Controller (initially on Cortex-A9)
device armgic: pic, pic_splfuncs
attach armgic at mpcorebus
diff -r 14a70db30d7d -r 23c279a18e24 sys/arch/arm/cortex/gic.c
--- a/sys/arch/arm/cortex/gic.c Sat Jun 25 13:20:30 2022 +0000
+++ b/sys/arch/arm/cortex/gic.c Sat Jun 25 13:24:34 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.54 2022/06/25 12:41:55 jmcneill Exp $ */
+/* $NetBSD: gic.c,v 1.55 2022/06/25 13:24:34 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -35,7 +35,7 @@
#define _INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.54 2022/06/25 12:41:55 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.55 2022/06/25 13:24:34 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -53,10 +53,6 @@
#include <arm/cortex/gic_reg.h>
#include <arm/cortex/mpcore_var.h>
-#ifdef GIC_SPLFUNCS
-#include <arm/cortex/gic_splfuncs.h>
-#endif
-
void armgic_irq_handler(void *);
#define ARMGIC_SGI_IPIBASE 0
@@ -745,10 +741,6 @@
aprint_normal_dev(sc->sc_dev, "%u Priorities, %zu SPIs, %u PPIs, "
"%u SGIs\n", priorities, sc->sc_gic_lines - ppis - sgis, ppis,
sgis);
-
-#ifdef GIC_SPLFUNCS
- gic_spl_init();
-#endif
}
CFATTACH_DECL_NEW(armgic, 0,
diff -r 14a70db30d7d -r 23c279a18e24 sys/arch/arm/cortex/gicv3.c
--- a/sys/arch/arm/cortex/gicv3.c Sat Jun 25 13:20:30 2022 +0000
+++ b/sys/arch/arm/cortex/gicv3.c Sat Jun 25 13:24:34 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.51 2022/06/25 12:41:55 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.52 2022/06/25 13:24:34 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.51 2022/06/25 12:41:55 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.52 2022/06/25 13:24:34 jmcneill Exp $");
#include <sys/param.h>
#include <sys/kernel.h>
@@ -53,10 +53,6 @@
#include <arm/cortex/gicv3.h>
#include <arm/cortex/gic_reg.h>
-#ifdef GIC_SPLFUNCS
-#include <arm/cortex/gic_splfuncs.h>
-#endif
-
#define PICTOSOFTC(pic) \
container_of(pic, struct gicv3_softc, sc_pic)
#define LPITOSOFTC(lpi) \
@@ -951,9 +947,5 @@
#endif
#endif
-#ifdef GIC_SPLFUNCS
- gic_spl_init();
-#endif
-
return 0;
}
diff -r 14a70db30d7d -r 23c279a18e24 sys/arch/arm/fdt/fdt_intr.h
--- a/sys/arch/arm/fdt/fdt_intr.h Sat Jun 25 13:20:30 2022 +0000
+++ b/sys/arch/arm/fdt/fdt_intr.h Sat Jun 25 13:24:34 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: fdt_intr.h,v 1.7 2021/09/20 21:05:15 jmcneill Exp $ */
+/* $NetBSD: fdt_intr.h,v 1.8 2022/06/25 13:24:34 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -40,10 +40,6 @@
#define PIC_MAXSOURCES 8192
#define PIC_MAXMAXSOURCES (PIC_MAXSOURCES * 2 + 32)
-#define _splraise pic_splraise
-#define _spllower pic_spllower
-#define splx pic_splx
-
void arm_fdt_irq_set_handler(void (*)(void *));
void arm_fdt_irq_handler(void *);
void arm_fdt_fiq_set_handler(void (*)(void *));
diff -r 14a70db30d7d -r 23c279a18e24 sys/arch/arm/gemini/gemini_intr.h
--- a/sys/arch/arm/gemini/gemini_intr.h Sat Jun 25 13:20:30 2022 +0000
+++ b/sys/arch/arm/gemini/gemini_intr.h Sat Jun 25 13:24:34 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: gemini_intr.h,v 1.3 2021/09/30 07:49:09 skrll Exp $ */
+/* $NetBSD: gemini_intr.h,v 1.4 2022/06/25 13:24:34 jmcneill Exp $ */
#ifndef _ARM_GEMINI_INTR_H_
#define _ARM_GEMINI_INTR_H_
@@ -8,10 +8,6 @@
#ifndef _LOCORE
void gemini_irq_handler(void *);
-#define _splraise pic_splraise
-#define _spllower pic_spllower
-#define splx pic_splx
-
#include <arm/pic/picvar.h>
#endif /* _LOCORE */
diff -r 14a70db30d7d -r 23c279a18e24 sys/arch/arm/imx/imx31_intr.h
--- a/sys/arch/arm/imx/imx31_intr.h Sat Jun 25 13:20:30 2022 +0000
+++ b/sys/arch/arm/imx/imx31_intr.h Sat Jun 25 13:24:34 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imx31_intr.h,v 1.5 2021/12/27 23:04:19 andvar Exp $ */
+/* $NetBSD: imx31_intr.h,v 1.6 2022/06/25 13:24:35 jmcneill Exp $ */
/*-
* Copyright (c) 2007 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -121,10 +121,6 @@
#define PIC_MAXMAXSOURCES (64+3*32+128)
-#define _splraise pic_splraise
-#define _spllower pic_spllower
-#define splx pic_splx
-
#include <arm/pic/picvar.h>
const char *
diff -r 14a70db30d7d -r 23c279a18e24 sys/arch/arm/imx/imx51_intr.h
--- a/sys/arch/arm/imx/imx51_intr.h Sat Jun 25 13:20:30 2022 +0000
+++ b/sys/arch/arm/imx/imx51_intr.h Sat Jun 25 13:24:34 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51_intr.h,v 1.2 2021/09/24 08:07:40 skrll Exp $ */
+/* $NetBSD: imx51_intr.h,v 1.3 2022/06/25 13:24:35 jmcneill Exp $ */
/*-
* Copyright (c) 2009 SHIMIZU Ryo <ryo%nerv.org@localhost>
* All rights reserved.
@@ -290,10 +290,6 @@
#define PIC_MAXSOURCES 128
#define PIC_MAXMAXSOURCES (PIC_MAXSOURCES+128)
-#define _splraise pic_splraise
-#define _spllower pic_spllower
-#define splx pic_splx
-
#include <arm/pic/picvar.h>
const char *intr_typename(int);
diff -r 14a70db30d7d -r 23c279a18e24 sys/arch/arm/marvell/mvsoc_intr.h
--- a/sys/arch/arm/marvell/mvsoc_intr.h Sat Jun 25 13:20:30 2022 +0000
+++ b/sys/arch/arm/marvell/mvsoc_intr.h Sat Jun 25 13:24:34 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsoc_intr.h,v 1.7 2021/09/24 08:07:40 skrll Exp $ */
+/* $NetBSD: mvsoc_intr.h,v 1.8 2022/06/25 13:24:35 jmcneill Exp $ */
/*
* Copyright (c) 2010 KIYOHARA Takashi
* All rights reserved.
@@ -45,10 +45,6 @@
void mvsoc_irq_handler(void *);
-#define _splraise pic_splraise
-#define _spllower pic_spllower
-#define splx pic_splx
-
#include <arm/pic/picvar.h>
static __inline void *
diff -r 14a70db30d7d -r 23c279a18e24 sys/arch/arm/omap/omap2_intr.h
--- a/sys/arch/arm/omap/omap2_intr.h Sat Jun 25 13:20:30 2022 +0000
+++ b/sys/arch/arm/omap/omap2_intr.h Sat Jun 25 13:24:34 2022 +0000
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