[src/trunk]: src/sys/arch/x86/x86 x86: Cite reference for bus_space_barrier m...

[riastradh <riastradh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/61c0b2af279a
branches:  trunk
changeset: 368511:61c0b2af279a
user:      riastradh <riastradh%NetBSD.org@localhost>
date:      Sun Jul 17 08:33:48 2022 +0000

description:
x86: Cite reference for bus_space_barrier memory ordering rules.

diffstat:

 sys/arch/x86/x86/bus_space.c |  12 ++++++++++--
 1 files changed, 10 insertions(+), 2 deletions(-)

diffs (33 lines):

diff -r e6e70ae03b79 -r 61c0b2af279a sys/arch/x86/x86/bus_space.c
--- a/sys/arch/x86/x86/bus_space.c      Sun Jul 17 05:51:29 2022 +0000
+++ b/sys/arch/x86/x86/bus_space.c      Sun Jul 17 08:33:48 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: bus_space.c,v 1.46 2021/10/07 12:52:27 msaitoh Exp $   */
+/*     $NetBSD: bus_space.c,v 1.47 2022/07/17 08:33:48 riastradh Exp $ */
 
 /*-
  * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bus_space.c,v 1.46 2021/10/07 12:52:27 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus_space.c,v 1.47 2022/07/17 08:33:48 riastradh Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -899,6 +899,14 @@
         * consulting the page tables), so just issue the fence
         * unconditionally.  Chances are either it's necessary or the
         * cost is small in comparison to device register I/O.
+        *
+        * Reference:
+        *
+        *      AMD64 Architecture Programmer's Manual, Volume 2:
+        *      System Programming, 24593--Rev. 3.38--November 2021,
+        *      Sec. 7.4.2 Memory Barrier Interaction with Memory
+        *      Types, Table 7-3, p. 196.
+        *      https://web.archive.org/web/20220625040004/https://www.amd.com/system/files/TechDocs/24593.pdf#page=256
         */
        switch (flags) {
        case 0: