[src/trunk]: src/sys/external/bsd/common/include/asm drm: Comment *mb() vs sm...

[riastradh <riastradh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/95cb14a4dd42
branches:  trunk
changeset: 368546:95cb14a4dd42
user:      riastradh <riastradh%NetBSD.org@localhost>
date:      Sun Jul 17 18:45:48 2022 +0000

description:
drm: Comment *mb() vs smp_*mb() and omit default for *mb().

In general membar_*() is _not_ enough for *mb(), because membar_*()
is only for CPU/CPU synchronization on normal memory, and *mb()
requires machine-dependent I/O logic.  Leave it as an `#error' case
if the architecture isn't listed here.  But membar_*() is OK for
smp_*().

Fill in powerpc and sparc while here, as examples of what the
now-removed defaults failed to do.  If you want to use drm on a mips
or alpha system yer gonna hafta fill this in yourself.

diffstat:

 sys/external/bsd/common/include/asm/barrier.h |  31 +++++++++++++++++++++++---
 1 files changed, 27 insertions(+), 4 deletions(-)

diffs (55 lines):

diff -r de2b5eccecd7 -r 95cb14a4dd42 sys/external/bsd/common/include/asm/barrier.h
--- a/sys/external/bsd/common/include/asm/barrier.h     Sun Jul 17 17:04:02 2022 +0000
+++ b/sys/external/bsd/common/include/asm/barrier.h     Sun Jul 17 18:45:48 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: barrier.h,v 1.13 2022/04/09 23:43:30 riastradh Exp $   */
+/*     $NetBSD: barrier.h,v 1.14 2022/07/17 18:45:48 riastradh Exp $   */
 
 /*-
  * Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -42,6 +42,14 @@
 #define        MULTIPROCESSOR  1       /* safer to assume multiprocessor */
 #endif
 
+/*
+ * I/O memory barriers.  drm uses these to order memory operations on
+ * normal or write-combining/prefetchable, or uncacheable I/O
+ * operations, for coordination between the CPU and I/O devices.
+ *
+ * In NetBSD, this is normally done with bus_space_barrier, but Linux
+ * doesn't pass around the bus space tag and handle needed for that.
+ */
 #if defined(__aarch64__)
 #define        mb()    __asm __volatile ("dsb sy" ::: "memory")
 #define        wmb()   __asm __volatile ("dsb st" ::: "memory")
@@ -51,12 +59,27 @@
 #define        mb()    x86_mfence()
 #define        wmb()   x86_sfence()
 #define        rmb()   x86_lfence()
+#elif defined(__powerpc__)
+#define        mb()    __asm __volatile ("eieio" ::: "memory")
+#define        wmb()   mb()
+#define        rmb()   mb()
+#elif defined(__sparc__) || defined(__sparc64__)
+#ifdef __sparc64__
+#define        mb()    __asm __volatile ("membar #MemIssue" ::: "memory")
 #else
-#define        mb      membar_sync
-#define        wmb     membar_producer
-#define        rmb     membar_consumer
+#define        mb()    membar_sync()   /* ldstub */
+#endif
+#define        wmb()   mb()            /* XXX could maybe be __insn_barrier in TSO */
+#define        rmb()   mb()            /* XXX could maybe be __insn_barrier in TSO */
+#else
+#error Define machine-dependent memory-mapped I/O barriers for drm.
 #endif
 
+/*
+ * MP memory barriers.  drm uses these to order memory operations on
+ * normal memory for coordination between CPUs.  Aliases for NetBSD's
+ * membar_*.
+ */
 #ifdef MULTIPROCESSOR
 #  define      smp_mb                          membar_sync
 #  define      smp_wmb                         membar_producer