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[src/trunk]: src/sys/arch Add initial support for RK3588 SoC (CRU and IOMUX)
details: https://anonhg.NetBSD.org/src/rev/0991488adfa0
branches: trunk
changeset: 369605:0991488adfa0
user: ryo <ryo%NetBSD.org@localhost>
date: Tue Aug 23 05:39:06 2022 +0000
description:
Add initial support for RK3588 SoC (CRU and IOMUX)
diffstat:
sys/arch/arm/rockchip/files.rockchip | 9 +-
sys/arch/arm/rockchip/rk3588_cru.c | 2936 ++++++++++++++++++++++++++++++
sys/arch/arm/rockchip/rk3588_cru.h | 754 +++++++
sys/arch/arm/rockchip/rk3588_iomux.c | 1040 ++++++++++
sys/arch/arm/rockchip/rk3588_platform.h | 40 +
sys/arch/arm/rockchip/rk_cru.h | 86 +-
sys/arch/arm/rockchip/rk_cru_arm.c | 8 +-
sys/arch/arm/rockchip/rk_cru_composite.c | 10 +-
sys/arch/arm/rockchip/rk_cru_pll.c | 141 +-
sys/arch/arm/rockchip/rk_platform.c | 64 +-
sys/arch/evbarm/conf/GENERIC64 | 4 +-
11 files changed, 5044 insertions(+), 48 deletions(-)
diffs (truncated from 5350 to 300 lines):
diff -r 7d742eae0e63 -r 0991488adfa0 sys/arch/arm/rockchip/files.rockchip
--- a/sys/arch/arm/rockchip/files.rockchip Tue Aug 23 05:33:39 2022 +0000
+++ b/sys/arch/arm/rockchip/files.rockchip Tue Aug 23 05:39:06 2022 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.rockchip,v 1.26 2022/07/20 10:01:11 riastradh Exp $
+# $NetBSD: files.rockchip,v 1.27 2022/08/23 05:39:06 ryo Exp $
#
# Configuration info for Rockchip family SoCs
#
@@ -35,6 +35,10 @@
attach rkcru at fdt with rk3399_pmucru
file arch/arm/rockchip/rk3399_pmucru.c rk3399_pmucru & soc_rk3399
+# RK3588 clock and reset unit
+attach rkcru at fdt with rk3588_cru
+file arch/arm/rockchip/rk3588_cru.c rk3588_cru & soc_rk3588
+
endif
# IOMUX control
@@ -51,6 +55,8 @@
file arch/arm/rockchip/rk3328_iomux.c rk3328_iomux & soc_rk3328
attach rkiomux at fdt with rk3399_iomux
file arch/arm/rockchip/rk3399_iomux.c rk3399_iomux & soc_rk3399
+attach rkiomux at fdt with rk3588_iomux
+file arch/arm/rockchip/rk3588_iomux.c rk3588_iomux & soc_rk3588
endif
@@ -155,3 +161,4 @@
defflag opt_soc.h SOC_RK3288: SOC_ROCKCHIP
defflag opt_soc.h SOC_RK3328: SOC_ROCKCHIP
defflag opt_soc.h SOC_RK3399: SOC_ROCKCHIP
+defflag opt_soc.h SOC_RK3588: SOC_ROCKCHIP
diff -r 7d742eae0e63 -r 0991488adfa0 sys/arch/arm/rockchip/rk3588_cru.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/rockchip/rk3588_cru.c Tue Aug 23 05:39:06 2022 +0000
@@ -0,0 +1,2936 @@
+/* $NetBSD: rk3588_cru.c,v 1.1 2022/08/23 05:39:06 ryo Exp $ */
+
+/*-
+ * Copyright (c) 2022 Ryo Shimizu <ryo%nerv.org@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: rk3588_cru.c,v 1.1 2022/08/23 05:39:06 ryo Exp $");
+
+#include <sys/param.h>
+#include <sys/device.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#include <arm/rockchip/rk_cru.h>
+#include <arm/rockchip/rk3588_cru.h>
+
+#define PLL_CON(base, n) (0x0000 + (base) + (n) * 4)
+#define MODE_CON(base, n) (0x0280 + (base) + (n) * 4)
+#define CLKSEL_CON(base, n) (0x0300 + (base) + (n) * 4)
+#define CLKGATE_CON(base, n) (0x0800 + (base) + (n) * 4)
+#define SOFTRST_CON(base, n) (0x0a00 + (base) + (n) * 4)
+/* base of above *_CON() macro */
+#define PHP 0x00008000
+#define PMU 0x00030000
+#define BIGCORE0 0x00050000
+#define BIGCORE1 0x00052000
+#define DSU 0x00058000
+
+#define RK3588_PHYREF_ALT_GATE 0x0c38
+
+static int rk3588_cru_match(device_t, cfdata_t, void *);
+static void rk3588_cru_attach(device_t, device_t, void *);
+
+static const struct device_compatible_entry compat_data[] = {
+ { .compat = "rockchip,rk3588-cru" },
+ DEVICE_COMPAT_EOL
+};
+
+CFATTACH_DECL_NEW(rk3588_cru, sizeof(struct rk_cru_softc),
+ rk3588_cru_match, rk3588_cru_attach, NULL, NULL);
+
+#define RK3588_CLK_CORE_L_SEL_MASK __BITS(6,5)
+#define RK3588_CLK_DSU_SEL_DF_MASK __BIT(15)
+#define RK3588_CLK_DSU_DF_SRC_MASK __BITS(6,5)
+#define RK3588_CLK_DSU_DF_DIV_MASK __BITS(4,0)
+#define RK3588_ACLKM_DSU_DIV_MASK __BITS(5,1)
+#define RK3588_ACLKS_DSU_DIV_MASK __BITS(10,6)
+#define RK3588_ACLKMP_DSU_DIV_MASK __BITS(15,11)
+#define RK3588_PERIPH_DSU_DIV_MASK __BITS(4,0)
+#define RK3588_ATCLK_DSU_DIV_MASK __BITS(4,0)
+#define RK3588_GICCLK_DSU_DIV_MASK __BITS(9,5)
+
+#define RK3588_CORE_L_SEL_CORE(regoff, apllcore) \
+ { \
+ .reg = CLKSEL_CON(DSU, 6 + (regoff)), \
+ .mask = RK3588_CLK_CORE_L_SEL_MASK, \
+ .val = __SHIFTIN((apllcore), RK3588_CLK_CORE_L_SEL_MASK)\
+ }
+
+#define RK3588_CORE_L_SEL_DSU(seldsu, divdsu) \
+ { \
+ .reg = CLKSEL_CON(DSU, 0), \
+ .mask = \
+ RK3588_CLK_DSU_DF_SRC_MASK | \
+ RK3588_CLK_DSU_DF_DIV_MASK | \
+ RK3588_CLK_DSU_SEL_DF_MASK, \
+ .val = \
+ __SHIFTIN((seldsu), RK3588_CLK_DSU_DF_SRC_MASK) | \
+ __SHIFTIN((divdsu) - 1, RK3588_CLK_DSU_DF_DIV_MASK) |\
+ __SHIFTIN(0, RK3588_CLK_DSU_SEL_DF_MASK) \
+ }
+
+#define RK3588_CORE_L_SEL_ACLKS(aclkm, aclkmp, aclks) \
+ { \
+ .reg = CLKSEL_CON(DSU, 1), \
+ .mask = \
+ RK3588_ACLKM_DSU_DIV_MASK | \
+ RK3588_ACLKMP_DSU_DIV_MASK | \
+ RK3588_ACLKS_DSU_DIV_MASK, \
+ .val = \
+ __SHIFTIN((aclkm) - 1, RK3588_ACLKM_DSU_DIV_MASK) | \
+ __SHIFTIN((aclkmp) - 1, RK3588_ACLKMP_DSU_DIV_MASK)|\
+ __SHIFTIN((aclks) - 1, RK3588_ACLKS_DSU_DIV_MASK) \
+ }
+
+#define RK3588_CORE_L_SEL_PERI(periph) \
+ { \
+ .reg = CLKSEL_CON(DSU, 2), \
+ .mask = RK3588_PERIPH_DSU_DIV_MASK, \
+ .val = __SHIFTIN((periph) - 1, RK3588_PERIPH_DSU_DIV_MASK)\
+ }
+
+#define RK3588_CORE_L_SEL_GIC_ATCLK(gicclk, atclk) \
+ { \
+ .reg = CLKSEL_CON(DSU, 3), \
+ .mask = \
+ RK3588_GICCLK_DSU_DIV_MASK | \
+ RK3588_ATCLK_DSU_DIV_MASK, \
+ .val = \
+ __SHIFTIN((gicclk) - 1, RK3588_GICCLK_DSU_DIV_MASK) |\
+ __SHIFTIN((atclk) - 1, RK3588_ATCLK_DSU_DIV_MASK) \
+ }
+
+#define RK3588_ARMCLK_L_RATE(targetrate, apllcore, seldsu, divdsu, \
+ atclk, gicclk, aclkmp, aclkm, aclks, periph) \
+ { \
+ .rate = (targetrate), \
+ .divs = { \
+ RK3588_CORE_L_SEL_DSU((seldsu), (divdsu)), \
+ RK3588_CORE_L_SEL_ACLKS((aclkm), (aclkmp), (aclks)),\
+ RK3588_CORE_L_SEL_PERI((periph)), \
+ RK3588_CORE_L_SEL_GIC_ATCLK((gicclk), (atclk)), \
+ }, \
+ .pre_muxs = { \
+ RK3588_CORE_L_SEL_CORE(0, 0), \
+ RK3588_CORE_L_SEL_CORE(1, 0), \
+ RK3588_CORE_L_SEL_DSU(3, 2), \
+ }, \
+ .post_muxs = { \
+ RK3588_CORE_L_SEL_CORE(0, (apllcore)), \
+ RK3588_CORE_L_SEL_CORE(1, (apllcore)), \
+ RK3588_CORE_L_SEL_DSU((seldsu), (divdsu)) \
+ }, \
+ }
+
+static const struct rk_cru_cpu_rate armclk_l_rates[] = {
+ RK3588_ARMCLK_L_RATE(2208000000, 1, 3, 1, 4, 4, 4, 4, 4, 4),
+ RK3588_ARMCLK_L_RATE(2184000000, 1, 3, 1, 4, 4, 4, 4, 4, 4),
+ RK3588_ARMCLK_L_RATE(2088000000, 1, 3, 1, 4, 4, 4, 4, 4, 4),
+ RK3588_ARMCLK_L_RATE(2040000000, 1, 3, 1, 4, 4, 4, 4, 4, 4),
+ RK3588_ARMCLK_L_RATE(2016000000, 1, 3, 1, 4, 4, 4, 4, 4, 4),
+ RK3588_ARMCLK_L_RATE(1992000000, 1, 3, 1, 4, 4, 4, 4, 4, 4),
+ RK3588_ARMCLK_L_RATE(1896000000, 1, 3, 1, 4, 4, 4, 4, 4, 4),
+ RK3588_ARMCLK_L_RATE(1800000000, 1, 3, 1, 4, 4, 4, 4, 4, 4),
+ RK3588_ARMCLK_L_RATE(1704000000, 0, 3, 1, 3, 3, 3, 3, 3, 3),
+ RK3588_ARMCLK_L_RATE(1608000000, 0, 3, 1, 3, 3, 3, 2, 3, 3),
+ RK3588_ARMCLK_L_RATE(1584000000, 0, 3, 1, 3, 3, 3, 2, 3, 3),
+ RK3588_ARMCLK_L_RATE(1560000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
+ RK3588_ARMCLK_L_RATE(1536000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
+ RK3588_ARMCLK_L_RATE(1512000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
+ RK3588_ARMCLK_L_RATE(1488000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
+ RK3588_ARMCLK_L_RATE(1464000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
+ RK3588_ARMCLK_L_RATE(1440000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
+ RK3588_ARMCLK_L_RATE(1416000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
+ RK3588_ARMCLK_L_RATE(1392000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
+ RK3588_ARMCLK_L_RATE(1368000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
+ RK3588_ARMCLK_L_RATE(1344000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
+ RK3588_ARMCLK_L_RATE(1320000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
+ RK3588_ARMCLK_L_RATE(1296000000, 0, 2, 2, 3, 3, 3, 2, 3, 3),
+ RK3588_ARMCLK_L_RATE(1272000000, 0, 2, 2, 2, 2, 2, 2, 2, 2),
+ RK3588_ARMCLK_L_RATE(1248000000, 0, 2, 2, 2, 2, 2, 2, 2, 2),
+ RK3588_ARMCLK_L_RATE(1224000000, 0, 2, 2, 2, 2, 2, 2, 2, 2),
+ RK3588_ARMCLK_L_RATE(1200000000, 0, 2, 2, 2, 2, 2, 2, 2, 2),
+ RK3588_ARMCLK_L_RATE(1104000000, 0, 2, 2, 2, 2, 2, 2, 2, 2),
+ RK3588_ARMCLK_L_RATE(1008000000, 0, 2, 2, 2, 2, 2, 2, 2, 2),
+ RK3588_ARMCLK_L_RATE( 912000000, 0, 2, 2, 2, 2, 2, 1, 2, 2),
+ RK3588_ARMCLK_L_RATE( 816000000, 0, 2, 2, 2, 2, 2, 1, 2, 2),
+ RK3588_ARMCLK_L_RATE( 696000000, 0, 2, 2, 2, 2, 2, 1, 2, 2),
+ RK3588_ARMCLK_L_RATE( 600000000, 0, 2, 1, 1, 1, 1, 1, 1, 1),
+ RK3588_ARMCLK_L_RATE( 408000000, 0, 2, 1, 1, 1, 1, 1, 1, 1),
+ RK3588_ARMCLK_L_RATE( 312000000, 0, 2, 1, 1, 1, 1, 1, 1, 1),
+ RK3588_ARMCLK_L_RATE( 216000000, 0, 2, 1, 1, 1, 1, 1, 1, 1),
+ RK3588_ARMCLK_L_RATE( 96000000, 0, 2, 1, 1, 1, 1, 1, 1, 1),
+};
+
+#define RK3588_CLK_CORE_B_SEL_MASK __BITS(14,13)
+#define RK3588_CLK_CORE_B_GPLL_DIV_MASK __BITS(5,1)
+
+#define RK3588_ARMCLK_B_RATE(_rate, _bigcore, _apllcore) \
+ { \
+ .rate = (_rate), \
+ .divs[0] = { \
+ .reg = CLKSEL_CON(_bigcore, 0), \
+ .mask = RK3588_CLK_CORE_B_SEL_MASK | \
+ RK3588_CLK_CORE_B_GPLL_DIV_MASK, \
+ .val = __SHIFTIN((_apllcore), \
+ RK3588_CLK_CORE_B_SEL_MASK) | \
+ __SHIFTIN(0, \
+ RK3588_CLK_CORE_B_GPLL_DIV_MASK) \
+ }, \
+ .divs[1] = { \
+ .reg = CLKSEL_CON(_bigcore, 1), \
+ .mask = RK3588_CLK_CORE_B_SEL_MASK, \
+ .val = __SHIFTIN((_apllcore), \
+ RK3588_CLK_CORE_B_SEL_MASK) \
+ } \
+ }
+
+static const struct rk_cru_cpu_rate armclk_b01_rates[] = {
+ RK3588_ARMCLK_B_RATE(2496000000, BIGCORE0, 1),
+ RK3588_ARMCLK_B_RATE(2400000000, BIGCORE0, 1),
+ RK3588_ARMCLK_B_RATE(2304000000, BIGCORE0, 1),
+ RK3588_ARMCLK_B_RATE(2208000000, BIGCORE0, 1),
+ RK3588_ARMCLK_B_RATE(2184000000, BIGCORE0, 1),
+ RK3588_ARMCLK_B_RATE(2088000000, BIGCORE0, 1),
+ RK3588_ARMCLK_B_RATE(2040000000, BIGCORE0, 1),
+ RK3588_ARMCLK_B_RATE(2016000000, BIGCORE0, 1),
+ RK3588_ARMCLK_B_RATE(1992000000, BIGCORE0, 1),
+ RK3588_ARMCLK_B_RATE(1896000000, BIGCORE0, 1),
+ RK3588_ARMCLK_B_RATE(1800000000, BIGCORE0, 1),
+ RK3588_ARMCLK_B_RATE(1704000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE(1608000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE(1584000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE(1560000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE(1536000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE(1512000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE(1488000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE(1464000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE(1440000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE(1416000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE(1392000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE(1368000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE(1344000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE(1320000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE(1296000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE(1272000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE(1248000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE(1224000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE(1200000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE(1104000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE(1008000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE( 912000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE( 816000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE( 696000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE( 600000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE( 408000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE( 312000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE( 216000000, BIGCORE0, 0),
+ RK3588_ARMCLK_B_RATE( 96000000, BIGCORE0, 0),
+};
+
+static const struct rk_cru_cpu_rate armclk_b23_rates[] = {
+ RK3588_ARMCLK_B_RATE(2496000000, BIGCORE1, 1),
+ RK3588_ARMCLK_B_RATE(2400000000, BIGCORE1, 1),
+ RK3588_ARMCLK_B_RATE(2304000000, BIGCORE1, 1),
+ RK3588_ARMCLK_B_RATE(2208000000, BIGCORE1, 1),
+ RK3588_ARMCLK_B_RATE(2184000000, BIGCORE1, 1),
+ RK3588_ARMCLK_B_RATE(2088000000, BIGCORE1, 1),
+ RK3588_ARMCLK_B_RATE(2040000000, BIGCORE1, 1),
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