[src/trunk]: src/sys/arch/powerpc/fpu Fix mtfsb[01]; these can clear/set any ...

[rin <rin%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/8adf029610fd
branches:  trunk
changeset: 369746:8adf029610fd
user:      rin <rin%NetBSD.org@localhost>
date:      Tue Aug 30 10:50:56 2022 +0000

description:
Fix mtfsb[01]; these can clear/set any FPSCR bits other than FEX and VX.

diffstat:

 sys/arch/powerpc/fpu/fpu_emu.c |  17 +++++++++--------
 1 files changed, 9 insertions(+), 8 deletions(-)

diffs (59 lines):

diff -r 84af4c8ba40f -r 8adf029610fd sys/arch/powerpc/fpu/fpu_emu.c
--- a/sys/arch/powerpc/fpu/fpu_emu.c    Tue Aug 30 10:48:31 2022 +0000
+++ b/sys/arch/powerpc/fpu/fpu_emu.c    Tue Aug 30 10:50:56 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: fpu_emu.c,v 1.38 2022/08/30 10:48:31 rin Exp $ */
+/*     $NetBSD: fpu_emu.c,v 1.39 2022/08/30 10:50:56 rin Exp $ */
 
 /*
  * Copyright 2001 Wasabi Systems, Inc.
@@ -76,7 +76,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: fpu_emu.c,v 1.38 2022/08/30 10:48:31 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fpu_emu.c,v 1.39 2022/08/30 10:50:56 rin Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_ddb.h"
@@ -289,7 +289,7 @@
        int ra, rb, rc, rt, type, mask, fsr, cx, bf, setcr;
        unsigned int cond;
        struct fpreg *fs;
-       int mtfsf = 0;
+       int mtfsf = 0, mtfsb1 = 0;
 
        /* Setup work. */
        fp = NULL;
@@ -513,8 +513,9 @@
                        case    OPC63_MTFSB1:
                                FPU_EMU_EVCNT_INCR(mtfsb1);
                                DPRINTF(FPE_INSN, ("fpu_execute: MTFSB1\n"));
-                               fe->fe_fpscr |= 
-                                       (~(FPSCR_VX|FPSR_EX) & (1<<(31-rt)));
+                               mtfsb1 = 1;
+                               fe->fe_cx = (1 << (31 - rt)) &
+                                   ~(FPSCR_FEX | FPSCR_VX);
                                break;
                        case    OPC63_FNEG:
                                FPU_EMU_EVCNT_INCR(fnegabs);
@@ -543,8 +544,8 @@
                        case    OPC63_MTFSB0:
                                FPU_EMU_EVCNT_INCR(mtfsb0);
                                DPRINTF(FPE_INSN, ("fpu_execute: MTFSB0\n"));
-                               fe->fe_fpscr &=
-                                       ((FPSCR_VX|FPSR_EX) & ~(1<<(31-rt)));
+                               fe->fe_fpscr &= ~(1 << (31 - rt)) |
+                                   (FPSCR_FEX | FPSCR_VX);
                                break;
                        case    OPC63_FMR:
                                FPU_EMU_EVCNT_INCR(fmr);
@@ -783,7 +784,7 @@
        cx = fe->fe_cx;
        fsr = fe->fe_fpscr & ~(FPSCR_FEX|FPSCR_VX);
        if (cx != 0) {
-               if (cx & FPSCR_FPRF) {
+               if (mtfsb1 == 0 && (cx & FPSCR_FPRF) != 0) {
                        /* Need to replace CC */
                        fsr &= ~FPSCR_FPRF;
                }