Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys/arch/x86/pci/imcsmb Fix compile error.
details: https://anonhg.NetBSD.org/src/rev/f4c754527ae5
branches: trunk
changeset: 371203:f4c754527ae5
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Wed Sep 28 10:09:48 2022 +0000
description:
Fix compile error.
diffstat:
sys/arch/x86/pci/imcsmb/imc.c | 12 ++++++------
1 files changed, 6 insertions(+), 6 deletions(-)
diffs (44 lines):
diff -r 5dbad76fc249 -r f4c754527ae5 sys/arch/x86/pci/imcsmb/imc.c
--- a/sys/arch/x86/pci/imcsmb/imc.c Wed Sep 28 09:57:13 2022 +0000
+++ b/sys/arch/x86/pci/imcsmb/imc.c Wed Sep 28 10:09:48 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imc.c,v 1.4 2021/08/07 16:19:08 thorpej Exp $ */
+/* $NetBSD: imc.c,v 1.5 2022/09/28 10:09:48 msaitoh Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -65,7 +65,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imc.c,v 1.4 2021/08/07 16:19:08 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imc.c,v 1.5 2022/09/28 10:09:48 msaitoh Exp $");
#include <sys/param.h>
#include <sys/kernel.h>
@@ -137,12 +137,12 @@
#define IMCSMB_PCI_DEV_ID_IMC0_SBX 0x3ca8
#define IMCSMB_PCI_DEV_ID_IMC0_IBX 0x0ea8
-#define IMCSMB_PCI_DEV_ID_IMC0_HSX PCI_PRODUCT_INTEL_XE5_V3_IMC0_MAIN
+#define IMCSMB_PCI_DEV_ID_IMC0_HSX PCI_PRODUCT_INTEL_XE5_V3_IMC0_TATRR
#define IMCSMB_PCI_DEV_ID_IMC0_BDX PCI_PRODUCT_INTEL_XEOND_MEM_0_TTR_1
/* (Sandy,Ivy)bridge-Xeon only have a single memory controller per socket */
-#define IMCSMB_PCI_DEV_ID_IMC1_HSX PCI_PRODUCT_INTEL_XE5_V3_IMC1_MAIN
+#define IMCSMB_PCI_DEV_ID_IMC1_HSX PCI_PRODUCT_INTEL_XE5_V3_IMC1_TATRR
#define IMCSMB_PCI_DEV_ID_IMC1_BDX PCI_PRODUCT_INTEL_COREI76K_IMC_0
/* There are two SMBus controllers in each device. These define the registers
@@ -291,8 +291,8 @@
switch(PCI_PRODUCT(pa->pa_id)) {
case PCI_PRODUCT_INTEL_COREI76K_IMC_0:
case PCI_PRODUCT_INTEL_XEOND_MEM_0_TTR_1:
- case PCI_PRODUCT_INTEL_XE5_V3_IMC0_MAIN:
- case PCI_PRODUCT_INTEL_XE5_V3_IMC1_MAIN:
+ case PCI_PRODUCT_INTEL_XE5_V3_IMC0_TATRR:
+ case PCI_PRODUCT_INTEL_XE5_V3_IMC1_TATRR:
case PCI_PRODUCT_INTEL_E5_IMC_TA:
case PCI_PRODUCT_INTEL_E5V2_IMC_TA:
return 1;
Home |
Main Index |
Thread Index |
Old Index