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[src/trunk]: src/sys/arch/arm Remove unused ARM11 MPCore code.
details: https://anonhg.NetBSD.org/src/rev/ce912271f19c
branches: trunk
changeset: 371865:ce912271f19c
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Sat Oct 15 11:31:40 2022 +0000
description:
Remove unused ARM11 MPCore code.
diffstat:
sys/arch/arm/Makefile.inc | 3 +-
sys/arch/arm/mpcore/dic.c | 356 ---------------------------------
sys/arch/arm/mpcore/dic_intr.h | 49 ----
sys/arch/arm/mpcore/dicreg.h | 89 --------
sys/arch/arm/mpcore/files.mpcore | 38 ---
sys/arch/arm/mpcore/mpcore_a2x_space.c | 129 -----------
sys/arch/arm/mpcore/mpcore_a4x_space.c | 129 -----------
sys/arch/arm/mpcore/mpcore_axi.c | 184 -----------------
sys/arch/arm/mpcore/mpcore_clock.c | 204 ------------------
sys/arch/arm/mpcore/mpcore_pmr.c | 119 -----------
sys/arch/arm/mpcore/mpcore_space.c | 266 ------------------------
sys/arch/arm/mpcore/mpcorereg.h | 78 -------
sys/arch/arm/mpcore/mpcorevar.h | 60 -----
13 files changed, 1 insertions(+), 1703 deletions(-)
diffs (truncated from 1766 to 300 lines):
diff -r cec1037534e2 -r ce912271f19c sys/arch/arm/Makefile.inc
--- a/sys/arch/arm/Makefile.inc Sat Oct 15 11:19:23 2022 +0000
+++ b/sys/arch/arm/Makefile.inc Sat Oct 15 11:31:40 2022 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile.inc,v 1.1 2011/04/04 19:43:34 dyoung Exp $
+# $NetBSD: Makefile.inc,v 1.2 2022/10/15 11:31:40 jmcneill Exp $
AARM= ${SYSDIR}/arch/arm/arm/*.S
SARM= ${SYSDIR}/arch/arm/arm/*.[ch] ${SYSDIR}/arch/arm/include/*.h
@@ -13,7 +13,6 @@
SARM+= ${SYSDIR}/arch/arm/ixp12x0/*.[ch]
SARM+= ${SYSDIR}/arch/arm/mainbus/*.[ch]
SARM+= ${SYSDIR}/arch/arm/marvell/*.[ch]
-SARM+= ${SYSDIR}/arch/arm/mpcore/*.[ch]
SARM+= ${SYSDIR}/arch/arm/ofw/*.[ch]
SARM+= ${SYSDIR}/arch/arm/omap/*.[ch]
SARM+= ${SYSDIR}/arch/arm/pic/*.[ch]
diff -r cec1037534e2 -r ce912271f19c sys/arch/arm/mpcore/dic.c
--- a/sys/arch/arm/mpcore/dic.c Sat Oct 15 11:19:23 2022 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,356 +0,0 @@
-/* $NetBSD: dic.c,v 1.3 2011/07/28 02:07:42 uebayasi Exp $ */
-
-/*
- * Copyright (c) 2010, 2011 Genetec Corporation. All rights reserved.
- * Written by Hiroyuki Bessho for Genetec Corporation.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: dic.c,v 1.3 2011/07/28 02:07:42 uebayasi Exp $");
-
-#define _INTR_PRIVATE /* for arm/pic/picvar.h */
-
-#include "locators.h"
-#include "opt_dic.h"
-
-#include <sys/param.h>
-#include <sys/evcnt.h>
-#include <sys/device.h>
-#include <sys/atomic.h>
-
-#include <machine/intr.h>
-#include <sys/bus.h>
-
-#include <uvm/uvm_extern.h>
-
-#include <arm/cpu.h>
-#include <arm/armreg.h>
-#include <arm/cpufunc.h>
-#include <arm/pic/picvar.h>
-
-#include <arm/mpcore/mpcorevar.h>
-#include <arm/mpcore/mpcorereg.h>
-#include <arm/mpcore/dicreg.h>
-
-#include <machine/autoconf.h>
-
-/*
- * 0 is the highest priority.
- */
-#define HW_TO_SW_IPL(ipl) (IPL_HIGH - (ipl))
-#define SW_TO_HW_IPL(ipl) (IPL_HIGH - (ipl))
-
-struct dic_softc {
- device_t sc_dev;
- struct pic_softc sc_pic;
- bus_space_tag_t sc_iot;
- bus_space_handle_t sc_cii_ioh;
- volatile uint32_t *sc_cii_vaddr; /* CPU interface */
- bus_space_handle_t sc_gid_ioh;
- volatile uint32_t *sc_gid_vaddr; /* Global distributor */
- int sc_nsrcs;
-// uint32_t sc_enabled_mask[4];
-};
-
-#define PIC_TO_SOFTC(pic) \
- ((struct dic_softc *)((char *)(pic) - \
- offsetof(struct dic_softc, sc_pic)))
-
-
-static int dic_match(device_t, cfdata_t, void *);
-static void dic_attach(device_t, device_t, void *);
-
-static void dic_unblock_irqs(struct pic_softc *, size_t, uint32_t);
-static void dic_block_irqs(struct pic_softc *, size_t, uint32_t);
-static void dic_establish_irq(struct pic_softc *, struct intrsource *);
-
-#define DIC_READ(sc, offset) \
- (*((sc)->sc_gid_vaddr + (offset) / sizeof (uint32_t)))
-#define DIC_WRITE(sc, offset, val) \
- (*((sc)->sc_gid_vaddr + (offset) / sizeof (uint32_t)) = (val))
-
-#define CII_READ(sc, offset) \
- (*((sc)->sc_cii_vaddr + (offset) / sizeof (uint32_t)))
-#define CII_WRITE(sc, offset, val) \
- (*((sc)->sc_cii_vaddr + (offset) / sizeof (uint32_t)) = (val))
-
-const struct pic_ops dic_pic_ops = {
- .pic_unblock_irqs = dic_unblock_irqs,
- .pic_block_irqs = dic_block_irqs,
- .pic_establish_irq = dic_establish_irq,
- .pic_source_name = NULL
-};
-
-
-CFATTACH_DECL_NEW(dic, sizeof(struct dic_softc),
- dic_match, dic_attach, NULL, NULL);
-
-struct dic_softc *dic_softc;
-
-static int
-dic_match(device_t parent, cfdata_t cf, void *aux)
-{
- if (strcmp(cf->cf_name, "dic") == 0)
- return 1;
-
- return 0;
-}
-
-
-static void
-dic_attach(device_t parent, device_t self, void *aux)
-{
- struct dic_softc *dic = device_private(self);
- struct pmr_attach_args * const pa = aux;
- uint32_t typ;
-
- aprint_normal(": Distributed Interrupt Controller\n");
- aprint_naive("\n");
-
- dic->sc_dev = self;
- dic->sc_iot = pa->pa_iot;
-
- dic_softc = dic;
-
- if (bus_space_subregion(dic->sc_iot, pa->pa_ioh,
- MPCORE_PMR_CII, MPCORE_PMR_CII_SIZE,
- &dic->sc_cii_ioh) ||
- bus_space_subregion(dic->sc_iot, pa->pa_ioh,
- MPCORE_PMR_GID, MPCORE_PMR_GID_SIZE,
- &dic->sc_gid_ioh)) {
-
- aprint_error_dev(self, "can't subregion\n");
- return;
- }
-
- dic->sc_cii_vaddr = bus_space_vaddr(dic->sc_iot, dic->sc_cii_ioh);
- dic->sc_gid_vaddr = bus_space_vaddr(dic->sc_iot, dic->sc_gid_ioh);
-
- typ = DIC_READ(dic, DIC_TYPE);
-
- dic->sc_nsrcs =
- 32 * (1 +
- ((typ & DIC_TYPE_NLINES_MASK) >> DIC_TYPE_NLINES_SHIFT));
-
- aprint_normal_dev(self, "%d CPUs, %d interrupt sources\n",
- 1 + (u_int)((typ & DIC_TYPE_NCPUS_MASK) >> DIC_TYPE_NCPUS_SHIFT),
- dic->sc_nsrcs);
-
-
- DIC_WRITE(dic, DIC_CONTROL, DIC_CONTROL_ENABLE);
-
- CII_WRITE(dic, CII_CONTROL, CII_CONTROL_ENABLE);
-
- dic->sc_pic.pic_ops = &dic_pic_ops;
- dic->sc_pic.pic_maxsources = dic->sc_nsrcs;
- strlcpy(dic->sc_pic.pic_name, device_xname(self),
- sizeof(dic->sc_pic.pic_name));
-
- pic_add(&dic->sc_pic, 0);
-
- enable_interrupts(I32_bit|F32_bit);
-}
-
-void
-dic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
-{
- struct dic_softc * const dic = PIC_TO_SOFTC(pic);
- size_t group = irq_base / 32;
-
- DIC_WRITE(dic, DIC_ENSET(group), irq_mask);
-}
-
-void
-dic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
-{
- struct dic_softc * const dic = PIC_TO_SOFTC(pic);
- size_t group = irq_base / 32;
-
- DIC_WRITE(dic, DIC_ENCLEAR(group), irq_mask);
-}
-
-static __inline u_int
-my_core_id(void)
-{
- uint32_t id;
-
- __asm ("mrc p15, 0, %0, c0, c0, 5" : "=r" (id));
-
- return id & 0x0f;
-}
-
-static void
-dic_establish_irq(struct pic_softc *pic, struct intrsource *is)
-{
- struct dic_softc * const dic = PIC_TO_SOFTC(pic);
- int irq = is->is_irq;
- int shift;
- int group;
- uint32_t reg;
-
- KASSERT(irq < dic->sc_nsrcs);
- KASSERT(is->is_ipl < 16);
-
-#ifdef NO_DIC_INITIALIZE
- /*
- * DIC is configured by the firmware.
- * don't change the settings.
- */
-#else
-
- group = irq / 4;
- shift = (irq % 4) * 8 + 4;
- reg = DIC_READ(dic, DIC_PRIORITY(group));
- reg &= ~(0xf << shift);
- reg |= SW_TO_HW_IPL(is->is_ipl) << shift;
- DIC_WRITE(dic, DIC_PRIORITY(group), reg);
-
- /* edge or level triggered.
- * always use 1-N interrupt software model.
- * XXX: limited to high-level or rising-edege trigger.
- */
- shift = (irq % 16) * 2;
- group = (irq / 16);
- reg = DIC_READ(dic, DIC_CONFIG(group));
- reg &= ~(0x03 << shift);
- if (is->is_type == IST_EDGE)
- reg |= 0x01 << shift;
- else
- reg |= 0x03 << shift;
- DIC_WRITE(dic, DIC_CONFIG(group), reg);
-
- group = irq / 4;
- shift = (irq % 4) * 8;
-
- reg = DIC_READ(dic, DIC_TARGET(group));
- reg &= ~(0x0f << shift);
-#ifdef MULTIPROCESSOR
-#error not yet.
-#else
- reg |= 1 << (my_core_id() + shift);
-#endif
- DIC_WRITE(dic, DIC_TARGET(group), reg);
-
-#endif /* NO_DIC_INITIALIZE */
-
- /* enable the interrupt */
- group = irq / 32;
- DIC_WRITE(dic, DIC_ENSET(group), 1 << (irq % 32));
-}
-
-void
-mpcore_irq_handler(void *frame)
-{
- struct cpu_info * const ci = curcpu();
- int irq;
- uint32_t reg, intack;
-
- ci->ci_data.cpu_nintr++;
-
- for (;;) {
- struct intrsource *is;
-
- intack = CII_READ(dic_softc, CII_INTACK);
- irq = intack & CII_INTACK_INTID_MASK;
-
- if (irq == 1023) /* spurious */
- break;
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