[src/trunk]: src/sys/arch/sparc64/sparc64 sparc64: Add missing barriers in cp...

[riastradh <riastradh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/a01eb8757e91
branches:  trunk
changeset: 373674:a01eb8757e91
user:      riastradh <riastradh%NetBSD.org@localhost>
date:      Thu Feb 23 14:56:56 2023 +0000

description:
sparc64: Add missing barriers in cpu_switchto.

Details in comments.

PR kern/57240

XXX pullup-8
XXX pullup-9
XXX pullup-10

diffstat:

 sys/arch/sparc64/sparc64/locore.s |  25 ++++++++++++++++++++++++-
 1 files changed, 24 insertions(+), 1 deletions(-)

diffs (58 lines):

diff -r 6afb837ecca9 -r a01eb8757e91 sys/arch/sparc64/sparc64/locore.s
--- a/sys/arch/sparc64/sparc64/locore.s Thu Feb 23 14:56:37 2023 +0000
+++ b/sys/arch/sparc64/sparc64/locore.s Thu Feb 23 14:56:56 2023 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.s,v 1.431 2022/07/05 20:15:40 andvar Exp $      */
+/*     $NetBSD: locore.s,v 1.432 2023/02/23 14:56:56 riastradh Exp $   */
 
 /*
  * Copyright (c) 2006-2010 Matthew R. Green
@@ -6731,9 +6731,28 @@
         * Load the new lwp.  To load, we must change stacks and
         * alter cpcb and the window control registers, hence we must
         * keep interrupts disabled.
+        *
+        * Issue barriers to coordinate mutex_exit on this CPU with
+        * mutex_vector_enter on another CPU.
+        *
+        * 1. Any prior mutex_exit by oldlwp must be visible to other
+        *    CPUs before we set ci_curlwp := newlwp on this one,
+        *    requiring a store-before-store barrier.
+        *
+        * 2. ci_curlwp := newlwp must be visible on all other CPUs
+        *    before any subsequent mutex_exit by newlwp can even test
+        *    whether there might be waiters, requiring a
+        *    store-before-load barrier.
+        *
+        * See kern_mutex.c for details -- this is necessary for
+        * adaptive mutexes to detect whether the lwp is on the CPU in
+        * order to safely block without requiring atomic r/m/w in
+        * mutex_exit.
         */
 
+       membar  #StoreStore
        STPTR   %i1, [%l7 + %lo(CURLWP)]        ! curlwp = l;
+       membar  #StoreLoad
        STPTR   %l1, [%l6 + %lo(CPCB)]          ! cpcb = newpcb;
 
        ldx     [%l1 + PCB_SP], %i6
@@ -6826,7 +6845,9 @@
        sethi   %hi(USPACE - TF_SIZE - CC64FSZ - STKB), %o3
        LDPTR   [%i0 + L_PCB], %l1              ! l1 = softint pcb
        or      %o3, %lo(USPACE - TF_SIZE - CC64FSZ - STKB), %o3
+       membar  #StoreStore             /* for mutex_enter; see cpu_switchto */
        STPTR   %i0, [%l7 + %lo(CURLWP)]
+       membar  #StoreLoad              /* for mutex_enter; see cpu_switchto */
        add     %l1, %o3, %i6
        STPTR   %l1, [%l6 + %lo(CPCB)]
        stx     %i6, [%l1 + PCB_SP]
@@ -6839,7 +6860,9 @@
 
        /* switch back to interrupted lwp */
        ldx     [%l5 + PCB_SP], %i6
+       membar  #StoreStore             /* for mutex_enter; see cpu_switchto */
        STPTR   %l0, [%l7 + %lo(CURLWP)]
+       membar  #StoreLoad              /* for mutex_enter; see cpu_switchto */
        STPTR   %l5, [%l6 + %lo(CPCB)]
 
        restore                                 ! rewind register window