[src/trunk]: src/sys/arch/mips/mips mips: Optimization: Omit needless membar ...

[riastradh <riastradh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/21a37e4266a2
branches:  trunk
changeset: 373790:21a37e4266a2
user:      riastradh <riastradh%NetBSD.org@localhost>
date:      Wed Mar 01 08:18:03 2023 +0000

description:
mips: Optimization: Omit needless membar when triggering softint.

When we are triggering a softint, it can't already hold any mutexes.
So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is
always done with atomic r/m/w, and we need not issue any explicit
barrier between ci->ci_curlwp = softlwp and a potential load of
mtx->mtx_owner in mutex_exit.

PR kern/57240

XXX pullup-8
XXX pullup-9
XXX pullup-10

diffstat:

 sys/arch/mips/mips/locore.S |  12 +++++++++---
 1 files changed, 9 insertions(+), 3 deletions(-)

diffs (33 lines):

diff -r 4bfbe8b2695d -r 21a37e4266a2 sys/arch/mips/mips/locore.S
--- a/sys/arch/mips/mips/locore.S       Wed Mar 01 08:17:53 2023 +0000
+++ b/sys/arch/mips/mips/locore.S       Wed Mar 01 08:18:03 2023 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.S,v 1.229 2023/02/23 14:56:00 riastradh Exp $   */
+/*     $NetBSD: locore.S,v 1.230 2023/03/01 08:18:03 riastradh Exp $   */
 
 /*
  * Copyright (c) 1992, 1993
@@ -63,7 +63,7 @@
 #include <mips/trap.h>
 #include <mips/locore.h>
 
-RCSID("$NetBSD: locore.S,v 1.229 2023/02/23 14:56:00 riastradh Exp $")
+RCSID("$NetBSD: locore.S,v 1.230 2023/03/01 08:18:03 riastradh Exp $")
 
 #include "assym.h"
 
@@ -429,7 +429,13 @@
        nop                                     # patchable load delay slot
        SYNC_PRODUCER /* XXX fixup */   /* for mutex_enter; see cpu_switchto */
        PTR_S   MIPS_CURLWP, CPU_INFO_CURLWP(s1)        #    ...
-       SYNC_DEKKER /* XXX fixup */     /* for mutex_enter; see cpu_switchto */
+       /*
+        * No need for barrier after ci->ci_curlwp = softlwp -- when we
+        * enter a softint lwp, it can't be holding any mutexes, so it
+        * can't release any until after it has acquired them, so we
+        * need not participate in the protocol with mutex_vector_enter
+        * barriers here.
+        */
        move    s2, sp                                  # remember sp
        move    s3, t0                                  # remember curpcb