[src/trunk]: src/sys/arch/sparc64/sparc64 sparc64: Optimization: Omit needles...

[riastradh <riastradh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/ec68e520a95a
branches:  trunk
changeset: 373793:ec68e520a95a
user:      riastradh <riastradh%NetBSD.org@localhost>
date:      Wed Mar 01 08:18:39 2023 +0000

description:
sparc64: Optimization: Omit needless membar when triggering softint.

When we are triggering a softint, it can't already hold any mutexes.
So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is
always done with atomic r/m/w, and we need not issue any explicit
barrier between ci->ci_curlwp = softlwp and a potential load of
mtx->mtx_owner in mutex_exit.

PR kern/57240

XXX pullup-8
XXX pullup-9
XXX pullup-10

diffstat:

 sys/arch/sparc64/sparc64/locore.s |  10 ++++++++--
 1 files changed, 8 insertions(+), 2 deletions(-)

diffs (24 lines):

diff -r deadb213fa5d -r ec68e520a95a sys/arch/sparc64/sparc64/locore.s
--- a/sys/arch/sparc64/sparc64/locore.s Wed Mar 01 08:18:24 2023 +0000
+++ b/sys/arch/sparc64/sparc64/locore.s Wed Mar 01 08:18:39 2023 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.s,v 1.432 2023/02/23 14:56:56 riastradh Exp $   */
+/*     $NetBSD: locore.s,v 1.433 2023/03/01 08:18:39 riastradh Exp $   */
 
 /*
  * Copyright (c) 2006-2010 Matthew R. Green
@@ -6847,7 +6847,13 @@
        or      %o3, %lo(USPACE - TF_SIZE - CC64FSZ - STKB), %o3
        membar  #StoreStore             /* for mutex_enter; see cpu_switchto */
        STPTR   %i0, [%l7 + %lo(CURLWP)]
-       membar  #StoreLoad              /* for mutex_enter; see cpu_switchto */
+       /*
+        * No need for barrier after ci->ci_curlwp = softlwp -- when we
+        * enter a softint lwp, it can't be holding any mutexes, so it
+        * can't release any until after it has acquired them, so we
+        * need not participate in the protocol with mutex_vector_enter
+        * barriers here.
+        */
        add     %l1, %o3, %i6
        STPTR   %l1, [%l6 + %lo(CPCB)]
        stx     %i6, [%l1 + PCB_SP]