[src/trunk]: src/sys/arch/mips/cavium/dev octrnm(4): Raise delay on startup.

[riastradh <riastradh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/dd8f821e90e6
branches:  trunk
changeset: 373945:dd8f821e90e6
user:      riastradh <riastradh%NetBSD.org@localhost>
date:      Tue Mar 21 22:07:29 2023 +0000

description:
octrnm(4): Raise delay on startup.

According to CN50XX-HRM-V0.99E and CN78XX-HM-0.99E:

   The entropy is provided by the jitter of 125 of 128 free-running
   oscillators XORed into a 128-bit LFSR.  The LFSR accumulates entropy
   over 81 cycles, after which it is fed into a SHA-1 engine.
   [...]
   The SHA-1 engine runs once every 81 cycles.
   [...]
   The hardware produces new 64-bit random number every 81 cycles.

The last sentence means that we only need to wait 81 cycles _between_
consecutive SHA-1 outputs (which isn't relevant anyway because we
reconfigure it into raw mode later), but the first two quotes might
mean that we need to wait 81+81 cycles for the _first_ output to be
produced on boot when running the self-test.

Now, in this case, the self-test is run with the LFSR unhooked, by
clearing the RNM_CTL_STATUS[ENT_EN] bit, so that SHA-1 is computed
from a known input -- this is really just paranoia to make sure that
_some_ functions of the device (which is conjured out of thin air at
a fixed virtual address, with no firmware bindings to guide us)
behave as we expect.

And it's not clear if it really does take 81+81 cycles for the first
SHA-1 output to appear when the LFSR isn't feeding into it anyway.
But experimentally, delay of 81+81 cycles seems to work whereas a
delay of only 81 cycles crashes.

PR kern/57280

XXX pullup-10
XXX pullup-9

diffstat:

 sys/arch/mips/cavium/dev/octeon_rnm.c |  9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)

diffs (37 lines):

diff -r ffebff01b46f -r dd8f821e90e6 sys/arch/mips/cavium/dev/octeon_rnm.c
--- a/sys/arch/mips/cavium/dev/octeon_rnm.c     Tue Mar 21 16:54:43 2023 +0000
+++ b/sys/arch/mips/cavium/dev/octeon_rnm.c     Tue Mar 21 22:07:29 2023 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: octeon_rnm.c,v 1.15 2022/03/19 11:55:03 riastradh Exp $        */
+/*     $NetBSD: octeon_rnm.c,v 1.16 2023/03/21 22:07:29 riastradh Exp $        */
 
 /*
  * Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -99,7 +99,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_rnm.c,v 1.15 2022/03/19 11:55:03 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_rnm.c,v 1.16 2023/03/21 22:07:29 riastradh Exp $");
 
 #include <sys/param.h>
 #include <sys/device.h>
@@ -119,7 +119,8 @@
 //#define      OCTRNM_DEBUG
 
 #define        ENT_DELAY_CLOCK 8       /* cycles for each 64-bit RO sample batch */
-#define        RNG_DELAY_CLOCK 81      /* cycles for each SHA-1 output */
+#define        LFSR_DELAY_CLOCK 81     /* cycles to fill LFSR buffer */
+#define        SHA1_DELAY_CLOCK 81     /* cycles to compute SHA-1 output */
 #define        NROGROUPS       16
 #define        RNG_FIFO_WORDS  (512/sizeof(uint64_t))
 
@@ -193,7 +194,7 @@
         */
        octrnm_reset(sc);
        octrnm_conditioned_deterministic(sc);
-       octrnm_delay(RNG_DELAY_CLOCK*1);
+       octrnm_delay(LFSR_DELAY_CLOCK + SHA1_DELAY_CLOCK);
        sample = octrnm_load(sc);
        if (sample != expected)
                aprint_error_dev(self, "self-test: read %016"PRIx64","