[src/trunk]: src/sys/arch s/Predective/Predictive/ and s/dedected/detected/ i...

[andvar <andvar%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/85476e803063
branches:  trunk
changeset: 374027:85476e803063
user:      andvar <andvar%NetBSD.org@localhost>
date:      Sat Mar 25 21:47:10 2023 +0000

description:
s/Predective/Predictive/ and s/dedected/detected/ in comments.

diffstat:

 sys/arch/atari/include/video.h    |  4 ++--
 sys/arch/x86/include/specialreg.h |  4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diffs (36 lines):

diff -r 898f814b6d78 -r 85476e803063 sys/arch/atari/include/video.h
--- a/sys/arch/atari/include/video.h    Sat Mar 25 21:35:49 2023 +0000
+++ b/sys/arch/atari/include/video.h    Sat Mar 25 21:47:10 2023 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: video.h,v 1.8 2022/07/03 11:30:48 andvar Exp $ */
+/*     $NetBSD: video.h,v 1.9 2023/03/25 21:47:10 andvar Exp $ */
 
 /*
  * Copyright (c) 1995 Leo Weppelman.
@@ -117,7 +117,7 @@ struct video {
 #define        TT_SHOLD        0x1000  /* Sample/hold mode                     */
 
 /* The falcon video modes */
-#define RES_FALAUTO    0       /* Falcon resolution dedected at boot   */
+#define RES_FALAUTO    0       /* Falcon resolution detected at boot   */
 #define RES_VGA2       1       /* 640x480,   2 colors                  */
 #define RES_VGA4       2       /* 640x480,   4 colors                  */
 #define RES_VGA16      3       /* 640x480,  16 colors                  */
diff -r 898f814b6d78 -r 85476e803063 sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Sat Mar 25 21:35:49 2023 +0000
+++ b/sys/arch/x86/include/specialreg.h Sat Mar 25 21:47:10 2023 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: specialreg.h,v 1.203 2023/02/17 09:53:24 msaitoh Exp $ */
+/*     $NetBSD: specialreg.h,v 1.204 2023/03/25 21:47:10 andvar Exp $  */
 
 /*
  * Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -1065,7 +1065,7 @@
 #define CPUID_AMDEXT2_FSRC       __BIT(11) /* Fast Short Rep Cmpsb */
 #define CPUID_AMDEXT2_PREFETCHCTL __BIT(13) /* Prefetch control MSR */
 #define CPUID_AMDEXT2_CPUIDUSRDIS __BIT(17) /* CPUID dis. for non-priv. soft */
-#define CPUID_AMDEXT2_EPSF       __BIT(18) /* Enhanced Predective Store Fwd */
+#define CPUID_AMDEXT2_EPSF       __BIT(18) /* Enhanced Predictive Store Fwd */
 
 #define CPUID_AMDEXT2_FLAGS     "\20"                                        \
        "\1NoNestedDataBp" "\2FsGsKernelGsBaseNonSerializing"                 \