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[src/trunk]: src/sys/arch/arm/nxp i.mx6sx CPU support in the CCM module: the ...
details: https://anonhg.NetBSD.org/src/rev/3ffdbc1361a1
branches: trunk
changeset: 374563:3ffdbc1361a1
user: bouyer <bouyer%NetBSD.org@localhost>
date: Thu May 04 13:25:07 2023 +0000
description:
i.mx6sx CPU support in the CCM module: the clock tree si different from
the i.mx6q
- move i.mx6q-specific functions and data to imx6_clk.c
- add i.mx6sx specific imx6sx_clk.c
- add a imx6sxccm device
diffstat:
sys/arch/arm/nxp/files.imx | 10 +-
sys/arch/arm/nxp/imx6_ccm.c | 35 +-
sys/arch/arm/nxp/imx6_ccmreg.h | 48 +-
sys/arch/arm/nxp/imx6_ccmvar.h | 12 +-
sys/arch/arm/nxp/imx6_clk.c | 20 +-
sys/arch/arm/nxp/imx6sx_clk.c | 1490 ++++++++++++++++++++++++++++++++++++++++
6 files changed, 1585 insertions(+), 30 deletions(-)
diffs (truncated from 1923 to 300 lines):
diff -r 2138bcefaebb -r 3ffdbc1361a1 sys/arch/arm/nxp/files.imx
--- a/sys/arch/arm/nxp/files.imx Thu May 04 11:30:25 2023 +0000
+++ b/sys/arch/arm/nxp/files.imx Thu May 04 13:25:07 2023 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.imx,v 1.2 2022/07/20 10:01:10 riastradh Exp $
+# $NetBSD: files.imx,v 1.3 2023/05/04 13:25:07 bouyer Exp $
#
# Configuration info for the Freescale i.MX6
#
@@ -10,6 +10,7 @@ defflag opt_soc.h SOC_IMX
defflag opt_soc.h SOC_IMX6DL: SOC_IMX
defflag opt_soc.h SOC_IMX6Q: SOC_IMX
defflag opt_soc.h SOC_IMX6QDL: SOC_IMX
+defflag opt_soc.h SOC_IMX6SX: SOC_IMX
defflag opt_soc.h SOC_IMX7D: SOC_IMX
defflag opt_imx.h IMX6
@@ -17,9 +18,14 @@ defflag opt_imx.h IMX6
# Clock
device imx6ccm : clk
attach imx6ccm at fdt
-file arch/arm/nxp/imx6_ccm.c imx6ccm
file arch/arm/nxp/imx6_clk.c imx6ccm
+device imx6sxccm : clk
+attach imx6sxccm at fdt
+file arch/arm/nxp/imx6sx_clk.c imx6sxccm
+
+file arch/arm/nxp/imx6_ccm.c imx6ccm | imx6sxccm
+
# Common FDT clock framework
define imx_ccm: clk
file arch/arm/nxp/imx_ccm.c imx_ccm
diff -r 2138bcefaebb -r 3ffdbc1361a1 sys/arch/arm/nxp/imx6_ccm.c
--- a/sys/arch/arm/nxp/imx6_ccm.c Thu May 04 11:30:25 2023 +0000
+++ b/sys/arch/arm/nxp/imx6_ccm.c Thu May 04 13:25:07 2023 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imx6_ccm.c,v 1.3 2023/04/14 17:45:59 bouyer Exp $ */
+/* $NetBSD: imx6_ccm.c,v 1.4 2023/05/04 13:25:07 bouyer Exp $ */
/*
* Copyright (c) 2010-2012, 2014 Genetec Corporation. All rights reserved.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx6_ccm.c,v 1.3 2023/04/14 17:45:59 bouyer Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx6_ccm.c,v 1.4 2023/05/04 13:25:07 bouyer Exp $");
#include "opt_imx.h"
#include "opt_cputypes.h"
@@ -52,7 +52,8 @@
#include <dev/clk/clk_backend.h>
-static void imxccm_init_clocks(struct imx6ccm_softc *);
+static void imxccm_init_clocks(struct imx6ccm_softc *,
+ struct imxccm_init_parent *);
static struct clk *imxccm_clk_get(void *, const char *);
static void imxccm_clk_put(void *, struct clk *);
static u_int imxccm_clk_get_rate(void *, struct clk *);
@@ -74,7 +75,8 @@ static const struct clk_funcs imxccm_clk
};
void
-imx6ccm_attach_common(device_t self, struct imx6_clk *imx6_clks, int size)
+imx6ccm_attach_common(device_t self, struct imx6_clk *imx6_clks, int size,
+ struct imxccm_init_parent *imxccm_init_parents)
{
struct imx6ccm_softc * const sc = device_private(self);
@@ -90,12 +92,13 @@ imx6ccm_attach_common(device_t self, str
clk_attach(&imx6_clks[n].base);
}
- imxccm_init_clocks(sc);
+ imxccm_init_clocks(sc, imxccm_init_parents);
for (int n = 0; n < size; n++) {
struct clk *clk = &imx6_clks[n].base;
struct clk *clk_parent = clk_get_parent(clk);
const char *parent_str = clk_parent ? clk_parent->name : "none";
+
aprint_verbose_dev(self, "%s (%s) : %u Hz\n", clk->name,
parent_str, clk_get_rate(clk));
}
@@ -127,27 +130,14 @@ imx6_clk_find(struct imx6ccm_softc *sc,
return NULL;
}
-struct imxccm_init_parent {
- const char *clock;
- const char *parent;
-} imxccm_init_parents[] = {
- { "pll1_bypass", "pll1" },
- { "pll2_bypass", "pll2" },
- { "pll3_bypass", "pll3" },
- { "pll4_bypass", "pll4" },
- { "pll5_bypass", "pll5" },
- { "pll6_bypass", "pll6" },
- { "pll7_bypass", "pll7" },
- { "lvds1_sel", "sata_ref_100m" },
-};
-
static void
-imxccm_init_clocks(struct imx6ccm_softc *sc)
+imxccm_init_clocks(struct imx6ccm_softc *sc,
+ struct imxccm_init_parent *imxccm_init_parents)
{
struct clk *clk;
struct clk *clk_parent;
- for (u_int n = 0; n < __arraycount(imxccm_init_parents); n++) {
+ for (u_int n = 0; imxccm_init_parents[n].clock != NULL; n++) {
clk = clk_get(&sc->sc_clkdom, imxccm_init_parents[n].clock);
KASSERT(clk != NULL);
clk_parent = clk_get(&sc->sc_clkdom, imxccm_init_parents[n].parent);
@@ -402,7 +392,8 @@ imxccm_clk_get_parent_mux(struct imx6ccm
uint32_t v = bus_space_read_4(sc->sc_iot, ioh, mux->reg);
u_int sel = __SHIFTOUT(v, mux->mask);
- KASSERT(sel < mux->nparents);
+ KASSERTMSG(sel < mux->nparents, "mux %s sel %d nparents %d",
+ iclk->base.name, sel, mux->nparents);
iclk->parent = mux->parents[sel];
diff -r 2138bcefaebb -r 3ffdbc1361a1 sys/arch/arm/nxp/imx6_ccmreg.h
--- a/sys/arch/arm/nxp/imx6_ccmreg.h Thu May 04 11:30:25 2023 +0000
+++ b/sys/arch/arm/nxp/imx6_ccmreg.h Thu May 04 13:25:07 2023 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imx6_ccmreg.h,v 1.1 2020/12/23 14:42:38 skrll Exp $ */
+/* $NetBSD: imx6_ccmreg.h,v 1.2 2023/05/04 13:25:07 bouyer Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -50,6 +50,12 @@
#ifndef IMX6_OSC_FREQ
#define IMX6_OSC_FREQ (24 * 1000 * 1000) /* 24MHz */
#endif
+#ifndef IMX6_IPP_DI0_FREQ
+#define IMX6_IPP_DI0_FREQ 0
+#endif
+#ifndef IMX6_IPP_DI1_FREQ
+#define IMX6_IPP_DI1_FREQ 0
+#endif
#ifndef IMX6_ANACLK1_FREQ
#define IMX6_ANACLK1_FREQ 0
#endif
@@ -115,6 +121,7 @@
#define CCM_CSCMR1 0x0000001c
#define CCM_CSCMR1_ACLK_EIM_SLOW_SEL __BITS(30, 29)
#define CCM_CSCMR1_ACLK_SEL __BITS(28, 27)
+#define CCM_CSCMR1_QSPI1_PODF __BITS(28, 26) /* 6sx */
#define CCM_CSCMR1_ACLK_EIM_SLOW_PODF __BITS(25, 23)
#define CCM_CSCMR1_ACLK_PODF __BITS(22, 20)
#define CCM_CSCMR1_USDHC4_CLK_SEL __BIT(19)
@@ -124,12 +131,17 @@
#define CCM_CSCMR1_SSI3_CLK_SEL __BITS(15, 14)
#define CCM_CSCMR1_SSI2_CLK_SEL __BITS(13, 12)
#define CCM_CSCMR1_SSI1_CLK_SEL __BITS(11, 10)
+#define CCM_CSCMR1_QSOI1_SEL __BITS(9, 7) /* 6sx */
+#define CCM_CSCMR1_PERCLK_SEL __BIT(6) /* 6sx */
#define CCM_CSCMR1_PERCLK_PODF __BITS(5, 0)
#define CCM_CSCMR2 0x00000020
+#define CCM_CSCMR2_VID_CLK_PODF __BITS(25, 24) /* 6sx */
+#define CCM_CSCMR2_VID_CLK_SEL __BITS(23, 21) /* 6sx */
#define CCM_CSCMR2_ESAI_CLK_SEL __BITS(20, 19)
#define CCM_CSCMR2_LDB_DI1_IPU_DIV __BIT(11)
#define CCM_CSCMR2_LDB_DI0_IPU_DIV __BIT(10)
+#define CCM_CSCMR2_CAN_CLK_SEL __BITS(9, 8) /* 6sx */
#define CCM_CSCMR2_CAN_CLK_PODF __BITS(7, 2)
#define CCM_CSCDR1 0x00000024
@@ -139,6 +151,7 @@
#define CCM_CSCDR1_USDHC2_PODF __BITS(18, 16)
#define CCM_CSCDR1_USDHC1_PODF __BITS(13, 11)
#define CCM_CSCDR1_UART_CLK_PODF __BITS(5, 0)
+#define CCM_CSCDR1_UART_CLK_SEL __BIT(6) /* 6sx */
#define CCM_CS1CDR 0x00000028
#define CCM_CS1CDR_ESAI_CLK_PODF __BITS(27, 25)
@@ -152,6 +165,7 @@
#define CCM_CS2CDR_ENFC_CLK_PODF __BITS(26, 21)
#define CCM_CS2CDR_ENFC_CLK_PRED __BITS(20, 18)
#define CCM_CS2CDR_ENFC_CLK_SEL __BITS(17, 16)
+#define CCM_CS2CDR_QSPI2_CLK_SEL __BITS(17, 15) /* 6sx */
#define CCM_CS2CDR_LDB_DI1_CLK_SEL __BITS(14, 12)
#define CCM_CS2CDR_LDB_DI0_CLK_SEL __BITS(11, 9)
#define CCM_CS2CDR_SSI2_CLK_PRED __BITS(8, 6)
@@ -168,15 +182,20 @@
#define CCM_CDCDR_SPDIF1_CLK_SEL __BITS(8, 7)
#define CCM_CHSCCDR 0x00000034
+#define CCM_CHSCCDR_ENET_PRE_CLK_SEL __BITS(17, 15) /* 6sx */
#define CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL __BITS(17, 15)
#define CCM_CHSCCDR_IPU1_DI1_PODF __BITS(14, 12)
+#define CCM_CHSCCDR_ENET_CLK_SEL __BITS(11, 9) /* 6sx */
#define CCM_CHSCCDR_IPU1_DI1_CLK_SEL __BITS(11, 9)
+#define CCM_CHSCCDR_M4_PRE_CLK_SEL __BITS(8, 6) /* 6sx */
#define CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL __BITS(8, 6)
#define CCM_CHSCCDR_IPU1_DI0_PODF __BITS(5, 3)
+#define CCM_CHSCCDR_M4_CLK_SEL __BITS(2, 0) /* 6sx */
#define CCM_CHSCCDR_IPU1_DI0_CLK_SEL __BITS(2, 0)
#define CCM_CSCDR2 0x00000038
#define CCM_CSCDR2_ECSPI_CLK_PODF __BITS(24, 19)
+#define CCM_CSCDR2_ECSPI_SEL __BIT(18) /* 6sx */
#define CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL __BITS(17, 15)
#define CCM_CSCDR2_IPU2_DI1_PODF __BITS(14, 12)
#define CCM_CSCDR2_IPU2_DI1_CLK_SEL __BITS(11, 9)
@@ -209,6 +228,7 @@
#define CCM_CCOSR_CLKO1_SEL __BITS(3, 0)
#define CCM_CCGR0 0x00000068
+#define CCM_CCGR0_TZ3_CLK_ENABLE __BITS(31, 30)
#define CCM_CCGR0_DTCP_CLK_ENABLE __BITS(29, 28)
#define CCM_CCGR0_DCIC2_CLK_ENABLE __BITS(27, 26)
#define CCM_CCGR0_DCIC1_CLK_ENABLE __BITS(25, 24)
@@ -225,10 +245,13 @@
#define CCM_CCGR0_AIPS_TZ2_CLK_ENABLE __BITS(3, 2)
#define CCM_CCGR0_AIPS_TZ1_CLK_ENABLE __BITS(1, 0)
#define CCM_CCGR1 0x0000006C
+#define CCM_CCGR1_CANFD_CLK_ENABLE __BITS(31, 30) /* 6sx */
+#define CCM_CCGR1_OCRAM_CLK_ENABLE __BITS(29, 28) /* 6sx */
#define CCM_CCGR1_GPU3D_CLK_ENABLE __BITS(27, 26)
#define CCM_CCGR1_GPU2D_CLK_ENABLE __BITS(25, 24)
#define CCM_CCGR1_GPT_SERIAL_CLK_ENABLE __BITS(23, 22)
#define CCM_CCGR1_GPT_CLK_ENABLE __BITS(21, 20)
+#define CCM_CCGR1_WAKEUP_CLK_ENABLE __BITS(19, 18) /* 6sx */
#define CCM_CCGR1_ESAI_CLK_ENABLE __BITS(17, 16)
#define CCM_CCGR1_EPIT2_CLK_ENABLE __BITS(15, 14)
#define CCM_CCGR1_EPIT1_CLK_ENABLE __BITS(13, 12)
@@ -240,6 +263,8 @@
#define CCM_CCGR1_ECSPI2_CLK_ENABLE __BITS(3, 2)
#define CCM_CCGR1_ECSPI1_CLK_ENABLE __BITS(1, 0)
#define CCM_CCGR2 0x00000070
+#define CCM_CCGR2_PXP_AXI_CLK_ENABLE __BITS(31, 30)
+#define CCM_CCGR2_LCDIF_APB_CLK_ENABLE __BITS(29, 28)
#define CCM_CCGR2_IPSYNC_VDOA_IPG_CLK_ENABLE __BITS(27, 26)
#define CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_CLK_ENABLE __BITS(25, 24)
#define CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPG_CLK_ENABLE __BITS(23, 22)
@@ -252,10 +277,12 @@
#define CCM_CCGR2_I2C2_SERIAL_CLK_ENABLE __BITS(9, 8)
#define CCM_CCGR2_I2C1_SERIAL_CLK_ENABLE __BITS(7, 6)
#define CCM_CCGR2_HDMI_TX_ISFRCLK_ENABLE __BITS(5, 4)
+#define CCM_CCGR2_CSI_CLK_ENABLE __BITS(3, 2) /* 6sx */
#define CCM_CCGR2_HDMI_TX_IAHBCLK_ENABLE __BITS(1, 0)
#define CCM_CCGR3 0x00000074
#define CCM_CCGR3_OPENVGAXICLK_CLK_ROOT_ENABLE __BITS(31, 30)
#define CCM_CCGR3_OCRAM_CLK_ENABLE __BITS(29, 28)
+#define CCM_CCGR3_MMDC_P1_IPG_CLK_ENABLE __BITS(27, 26) /* 6sx */
#define CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_ENABLE __BITS(25, 24)
#define CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_ENABLE __BITS(23, 22)
#define CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_ENABLE __BITS(21, 20)
@@ -280,9 +307,12 @@
#define CCM_CCGR4_PWM1_CLK_ENABLE __BITS(17, 16)
#define CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE __BITS(15, 14)
#define CCM_CCGR4_PL301_MX6QPER1_BCHCLK_ENABLE __BITS(13, 12)
+#define CCM_CCGR4_QSPI2_ENABLE __BITS(11, 10) /*6sx*/
#define CCM_CCGR4_PL301_MX6QFAST1_S133CLK_ENABLE __BITS(9, 8)
#define CCM_CCGR4_PCIE_ROOT_ENABLE __BITS(1, 0)
#define CCM_CCGR5 0x0000007c
+#define CCM_CCGR5_SAI2_ENABLE __BITS(31, 30) /* 6sx */
+#define CCM_CCGR5_SAI1_ENABLE __BITS(29, 28) /* 6sx */
#define CCM_CCGR5_UART_SERIAL_CLK_ENABLE __BITS(27, 26)
#define CCM_CCGR5_UART_CLK_ENABLE __BITS(25, 24)
#define CCM_CCGR5_SSI3_CLK_ENABLE __BITS(23, 22)
@@ -294,6 +324,13 @@
#define CCM_CCGR5_SATA_CLK_ENABLE __BITS(5, 4)
#define CCM_CCGR5_ROM_CLK_ENABLE __BITS(1, 0)
#define CCM_CCGR6 0x00000080
+#define CCM_CCGR6_PWM7_CLK_ENABLE __BITS(31, 30) /* 6sx */
+#define CCM_CCGR6_PWM6_CLK_ENABLE __BITS(29, 28) /* 6sx */
+#define CCM_CCGR6_PWM5_CLK_ENABLE __BITS(27, 26) /* 6sx */
+#define CCM_CCGR6_I2CS4_CLK_ENABLE __BITS(25, 24) /* 6sx */
+#define CCM_CCGR6_GIS_CLK_ENABLE __BITS(23, 22) /* 6sx */
+#define CCM_CCGR6_VADC_CLK_ENABLE __BITS(21, 20) /* 6sx */
+#define CCM_CCGR6_PWM8_CLK_ENABLE __BITS(17, 16) /* 6sx */
#define CCM_CCGR6_VPU_CLK_ENABLE __BITS(15, 14)
#define CCM_CCGR6_VDOAXICLK_CLK_ENABLE __BITS(13, 12)
#define CCM_CCGR6_EIM_SLOW_CLK_ENABLE __BITS(11, 10)
@@ -316,6 +353,7 @@
#define CCM_ANALOG_PLL_ARM_LVDS_SEL __BIT(17)
#define CCM_ANALOG_PLL_ARM_BYPASS __BIT(16)
#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC __BITS(15, 14)
+#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_6SX __BIT(14) /* 6sx */
#define CCM_ANALOG_PLL_ARM_ENABLE __BIT(13)
#define CCM_ANALOG_PLL_ARM_POWERDOWN __BIT(12)
#define CCM_ANALOG_PLL_ARM_DIV_SELECT __BITS(6, 0)
@@ -323,6 +361,7 @@
#define CCM_ANALOG_PLL_LOCK __BIT(31)
#define CCM_ANALOG_PLL_BYPASS __BIT(16)
#define CCM_ANALOG_PLL_BYPASS_CLK_SRC __BITS(15, 14)
+#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_6SX __BIT(14)
#define CCM_ANALOG_PLL_ENABLE __BIT(13)
#define CCM_ANALOG_PLL_POWER __BIT(12)
#define CCM_ANALOG_PLL_EN_USB_CLK __BIT(6)
@@ -336,6 +375,7 @@
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