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[src/trunk]: src/sys/arch/arm/sociox small fixes, code shuffle for ease of un...



details:   https://anonhg.NetBSD.org/src/rev/0bfcecc4a955
branches:  trunk
changeset: 375910:0bfcecc4a955
user:      nisimura <nisimura%NetBSD.org@localhost>
date:      Sun May 21 00:35:38 2023 +0000

description:
small fixes, code shuffle for ease of understanding.

diffstat:

 sys/arch/arm/sociox/if_scx.c |  493 +++++++++++++++++++++++++++---------------
 1 files changed, 313 insertions(+), 180 deletions(-)

diffs (truncated from 959 to 300 lines):

diff -r b68b2badc02d -r 0bfcecc4a955 sys/arch/arm/sociox/if_scx.c
--- a/sys/arch/arm/sociox/if_scx.c      Sat May 20 22:08:07 2023 +0000
+++ b/sys/arch/arm/sociox/if_scx.c      Sun May 21 00:35:38 2023 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_scx.c,v 1.39 2022/09/27 06:36:43 skrll Exp $        */
+/*     $NetBSD: if_scx.c,v 1.40 2023/05/21 00:35:38 nisimura Exp $     */
 
 /*-
  * Copyright (c) 2020 The NetBSD Foundation, Inc.
@@ -29,6 +29,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
+#define NOT_MP_SAFE    0
 
 /*
  * Socionext SC2A11 SynQuacer NetSec GbE driver
@@ -41,17 +42,14 @@
  * NetSec uses Synopsys DesignWare Core EMAC.  DWC implementation
  * register (0x20) is known to have 0x10.36 and feature register (0x1058)
  * reports 0x11056f37.
- *  <24> exdesc
+ *  <24> alternative/enhanced desc format
  *  <18> receive IP type 2 checksum offload
- *  <17> (no) receive IP type 1 checksum offload
  *  <16> transmit checksum offload
  *  <11> event counter (mac management counter, MMC) 
  */
 
-#define NOT_MP_SAFE    0
-
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.39 2022/09/27 06:36:43 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.40 2023/05/21 00:35:38 nisimura Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -81,27 +79,25 @@
 struct tdes {
        uint32_t t0, t1, t2, t3;
 };
-
 struct rdes {
        uint32_t r0, r1, r2, r3;
 };
-
 #define T0_OWN         (1U<<31)        /* desc is ready to Tx */
-#define T0_EOD         (1U<<30)        /* end of descriptor array */
+#define T0_LD          (1U<<30)        /* last descriptor in array */
 #define T0_DRID                (24)            /* 29:24 desc ring id */
 #define T0_PT          (1U<<21)        /* 23:21 "pass-through" */
 #define T0_TDRID       (16)            /* 20:16 target desc ring id: GMAC=15 */
+#define T0_CC          (1U<<15)        /* ??? */
 #define T0_FS          (1U<<9)         /* first segment of frame */
 #define T0_LS          (1U<<8)         /* last segment of frame */
 #define T0_CSUM                (1U<<7)         /* enable check sum offload */
 #define T0_TSO         (1U<<6)         /* enable TCP segment offload */
-#define T0_TRS         (1U<<4)         /* 5:4 "TRS" */
+#define T0_TRS         (1U<<4)         /* 5:4 "TRS" ??? */
 /* T1 frame segment address 63:32 */
 /* T2 frame segment address 31:0 */
 /* T3 31:16 TCP segment length, 15:0 frame segment length to transmit */
-
 #define R0_OWN         (1U<<31)        /* desc is empty */
-#define R0_EOD         (1U<<30)        /* end of descriptor array */
+#define R0_LD          (1U<<30)        /* last descriptor in array */
 #define R0_SDRID       (24)            /* 29:24 source desc ring id */
 #define R0_FR          (1U<<23)        /* found fragmented */
 #define R0_ER          (1U<<21)        /* Rx error indication */
@@ -131,9 +127,13 @@ struct rdes {
 #define  RPTHDERR      (1U<<1)         /* log HD error */
 #define  DROPNOMATCH   (1U<<0)         /* drop no match frames */
 #define xINTSR         0x200           /* aggregated interrupt status */
+#define  IRQ_UCODE     (1U<<20)        /* ucode load completed; W1C */
+#define  IRQ_MAC       (1U<<19)        /* ??? */
+#define  IRQ_PKT       (1U<<18)        /* ??? */
+#define  IRQ_BOOTCODE  (1U<<5)         /* ??? */
+#define  IRQ_XDONE     (1U<<4)         /* ??? mode change completed */
 #define  IRQ_RX                (1U<<1)         /* top level Rx interrupt */
-#define  IRQ_TX                (1U<<0)         /* top level Rx interrupt */
-#define  IRQ_UCODE     (1U<<20)        /* ucode load completed; W1C */
+#define  IRQ_TX                (1U<<0)         /* top level Tx interrupt */
 #define xINTAEN                0x204           /* INT_A enable */
 #define xINTAE_SET     0x234           /* bit to set */
 #define xINTAE_CLR     0x238           /* bit to clr */
@@ -174,6 +174,7 @@ struct rdes {
 #define RXITIMER       0x460           /* coalesce timer usec, MSB to use */
 #define TXDONECNT      0x414           /* tx completed count, auto-zero */
 #define RXDONECNT      0x454           /* rx available count, auto-zero */
+#define DMACTL_TMR     0x20c           /* engine DMA timer value */
 #define UCODE_H2M      0x210           /* host2media engine ucode port */
 #define UCODE_M2H      0x21c           /* media2host engine ucode port */
 #define CORESTAT       0x218           /* engine run state */
@@ -223,9 +224,9 @@ struct rdes {
 #define  MCR_WD                (1U<<23)        /* allow long >2048 tx frame */
 #define  MCR_JE                (1U<<20)        /* allow ~9018 tx jumbo frame */
 #define  MCR_IFG       (7U<<17)        /* 19:17 IFG value 0~7 */
-#define  MCR_DRCS      (1U<<16)        /* ignore (G)MII HDX Tx error */
-#define  MCR_USEMII    (1U<<15)        /* 1: RMII/MII, 0: RGMII (_PS) */
-#define  MCR_SPD100    (1U<<14)        /* force speed 100 (_FES) */
+#define  MCR_DCRS      (1U<<16)        /* ignore (G)MII HDX Tx error */
+#define  MCR_PS                (1U<<15)        /* 1: MII 10/100, 0: GMII 1000 */
+#define  MCR_FES       (1U<<14)        /* force speed 100 */
 #define  MCR_DO                (1U<<13)        /* don't receive my own HDX Tx frames */
 #define  MCR_LOOP      (1U<<12)        /* run loop back */
 #define  MCR_USEFDX    (1U<<11)        /* force full duplex */
@@ -233,11 +234,10 @@ struct rdes {
 #define  MCR_DR                (1U<<9)         /* attempt no tx retry, send once */
 #define  MCR_LUD       (1U<<8)         /* link condition report when RGMII */
 #define  MCR_ACS       (1U<<7)         /* auto pad strip CRC */
+#define  MCR_DC                (1U<<4)         /* report excessive tx deferral */
 #define  MCR_TE                (1U<<3)         /* run Tx MAC engine, 0 to stop */
 #define  MCR_RE                (1U<<2)         /* run Rx MAC engine, 0 to stop */
 #define  MCR_PREA      (3U)            /* 1:0 preamble len. 0~2 */
-#define  _MCR_FDX      0x0000280c      /* XXX TBD */
-#define  _MCR_HDX      0x0001a00c      /* XXX TBD */
 #define GMACAFR                0x0004          /* frame DA/SA address filter */
 #define  AFR_RA                (1U<<31)        /* accept all irrespective of filt. */
 #define  AFR_HPF       (1U<<10)        /* hash+perfect filter, or hash only */
@@ -267,7 +267,7 @@ struct rdes {
 /* 31:16 pause timer value, 5:4 pause timer threshold */
 #define  FCR_RFE       (1U<<2)         /* accept PAUSE to throttle Tx */
 #define  FCR_TFE       (1U<<1)         /* generate PAUSE to moderate Rx lvl */
-#define GMACIMPL       0x0020          /* implementation id XX.YY (no use) */
+#define GMACIMPL       0x0020          /* implementation id */
 #define GMACISR                0x0038          /* interrupt status indication */
 #define GMACIMR                0x003c          /* interrupt mask to inhibit */
 #define  ISR_TS                (1U<<9)         /* time stamp operation detected */
@@ -287,14 +287,14 @@ struct rdes {
 #define GMACMHTH       0x0008          /* 64bit multicast hash table 63:32 */
 #define GMACMHTL       0x000c          /* 64bit multicast hash table 31:0 */
 #define GMACMHT(i)     ((i)*4+0x500)   /* 256-bit alternative mcast hash 0-7 */
-#define EMACVTAG       0x001c          /* VLAN tag control */
+#define GMACVTAG       0x001c          /* VLAN tag control */
 #define  VTAG_HASH     (1U<<19)        /* use VLAN tag hash table */
 #define  VTAG_SVLAN    (1U<<18)        /* handle type 0x88A8 SVLAN frame */
 #define  VTAG_INV      (1U<<17)        /* run inverse match logic */
 #define  VTAG_ETV      (1U<<16)        /* use only 12bit VID field to match */
 /* 15:0 concat of PRIO+CFI+VID */
 #define GMACVHT                0x0588          /* 16-bit VLAN tag hash */
-#define GMACMIISR      0x00d8          /* resolved xMII link status */
+#define GMACMIISR      0x00d8          /* resolved RGMII/SGMII link status */
 #define  MIISR_LUP     (1U<<3)         /* link up(1)/down(0) report */
 #define  MIISR_SPD     (3U<<1)         /* 2:1 speed 10(0)/100(1)/1000(2) */
 #define  MIISR_FDX     (1U<<0)         /* fdx detected */
@@ -307,37 +307,28 @@ struct rdes {
 #define GMACLPIC       0x0034          /* LPI timer control */
 #define  LPIC_LST      (5)             /* 16:5 ??? */
 #define  LPIC_TWT      (0)             /* 15:0 ??? */
-#define GMACTSC                0x0700          /* timestamp control */
-#define GMACSTM                0x071c          /* start time */
-#define GMACTGT                0x0720          /* target time */
-#define GMACTSS                0x0728          /* timestamp status */
-#define GMACPPS                0x072c          /* PPS control */
-#define GMACPPS0       0x0764          /* PPS0 width */
+/* 0x700-764 Time Stamp control */
 
 #define GMACBMR                0x1000          /* DMA bus mode control */
-/* 24    multiply by x8 for RPBL & PBL values
- * 23    use RPBL for Rx DMA
+/* 24    8xPBL multiply by 8 for RPBL & PBL values
+ * 23    USP 1 to use RPBL for Rx DMA burst, 0 to share PBL by Rx and Tx
  * 22:17 RPBL
- * 16    fixed burst
+ * 16    FB fixed burst
  * 15:14 priority between Rx and Tx
  *  3    rxtx ratio 41
  *  2    rxtx ratio 31
  *  1    rxtx ratio 21
  *  0    rxtx ratio 11
  * 13:8  PBL possible DMA burst length
- *  7    select alternative 32-byte descriptor format for new features
- *  6:2  descriptor spacing. 0 for adjuscent
- *  0    GMAC reset op. self-clear
+ *  7    ATDS select 32-byte descriptor format for advanced features
+ *  6:2         DSL descriptor skip length, 0 for adjuscent, counted on bus width
+ *  0    MAC reset op. self-clear
  */
-#define  _BMR          0x00412080      /* XXX TBD */
-#define  _BMR0         0x00020181      /* XXX TBD */
 #define  BMR_RST       (1)             /* reset op. self clear when done */
 #define GMACTPD                0x1004          /* write any to resume tdes */
 #define GMACRPD                0x1008          /* write any to resume rdes */
 #define GMACRDLA       0x100c          /* rdes base address 32bit paddr */
 #define GMACTDLA       0x1010          /* tdes base address 32bit paddr */
-#define  _RDLA         0x18000         /* system RAM for GMAC rdes */
-#define  _TDLA         0x1c000         /* system RAM for GMAC tdes */
 #define GMACDSR                0x1014          /* DMA status detail report; W1C */
 #define GMACDIE                0x101c          /* DMA interrupt enable */
 #define  DMAI_LPI      (1U<<30)        /* LPI interrupt */
@@ -380,7 +371,7 @@ struct rdes {
 /* 0x1050 current tx buffer address */
 /* 0x1054 current rx buffer address */
 #define HWFEA          0x1058          /* DWC feature report */
-#define  FEA_EXDESC    (1U<<24)        /* new desc layout */
+#define  FEA_EXDESC    (1U<<24)        /* alternative/enhanced desc layout */
 #define  FEA_2COE      (1U<<18)        /* Rx type 2 IP checksum offload */
 #define  FEA_1COE      (1U<<17)        /* Rx type 1 IP checksum offload */
 #define  FEA_TXOE      (1U<<16)        /* Tx checksum offload */
@@ -395,6 +386,8 @@ struct rdes {
 #define  EVC_CR                (1U<<0)         /* reset counters */
 #define GMACEVCNT(i)   ((i)*4+0x114)   /* 80 event counters 0x114 - 0x284 */
 
+/* 0x400-4ac L3/L4 control */
+
 /*
  * flash memory layout
  * 0x00 - 07   48-bit MAC station address. 4 byte wise in BE order.
@@ -410,19 +403,28 @@ struct rdes {
  * above ucode are loaded via mapped reg 0x210, 0x21c and 0x0c0.
  */
 
+#define  _BMR          0x00412080      /* XXX TBD */
+#define  _BMR0         0x00020181      /* XXX TBD */
+/* NetSec uses local RAM to handle GMAC desc arrays and frame buffers */
+#define  _RDLA         0x18000
+#define  _TDLA         0x1c000
+#define  _MCR_FDX      0x0000280c      /* XXX TBD */
+#define  _MCR_HDX      0x0001a00c      /* XXX TBD */
+
 /*
  * all below are software constraction.
  */
-#define MD_NTXSEGS             16              /* fixed */
-#define MD_TXQUEUELEN          8               /* tunable */
+#define MD_NTXDESC             128
+#define MD_NRXDESC             64
+
+#define MD_NTXSEGS             16
+#define MD_TXQUEUELEN          8
 #define MD_TXQUEUELEN_MASK     (MD_TXQUEUELEN - 1)
 #define MD_TXQUEUE_GC          (MD_TXQUEUELEN / 4)
-#define MD_NTXDESC             128
 #define MD_NTXDESC_MASK        (MD_NTXDESC - 1)
 #define MD_NEXTTX(x)           (((x) + 1) & MD_NTXDESC_MASK)
 #define MD_NEXTTXS(x)          (((x) + 1) & MD_TXQUEUELEN_MASK)
 
-#define MD_NRXDESC             64              /* tunable */
 #define MD_NRXDESC_MASK        (MD_NRXDESC - 1)
 #define MD_NEXTRX(x)           (((x) + 1) & MD_NRXDESC_MASK)
 
@@ -465,9 +467,10 @@ struct scx_softc {
        int sc_flowflags;               /* 802.3x PAUSE flow control */
        uint32_t sc_mdclk;              /* GAR 5:2 clock selection */
        uint32_t sc_t0cotso;            /* T0_CSUM | T0_TSO to run */
-       int sc_100mii;                  /* 1 for RMII/MII, 0 for RGMII */
+       int sc_miigmii;                 /* 1: MII/GMII, 0: RGMII */
        int sc_phandle;                 /* fdt phandle */
        uint64_t sc_freq;
+       uint32_t sc_maxsize;
 
        bus_dmamap_t sc_cddmamap;       /* control data DMA map */
 #define sc_cddma       sc_cddmamap->dm_segs[0].ds_addr
@@ -526,13 +529,14 @@ do {                                                                      \
        struct scx_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)];               \
        struct rdes *__rxd = &(sc)->sc_rxdescs[(x)];                    \
        struct mbuf *__m = __rxs->rxs_mbuf;                             \
-       bus_addr_t __paddr =__rxs->rxs_dmamap->dm_segs[0].ds_addr;      \
+       bus_addr_t __p = __rxs->rxs_dmamap->dm_segs[0].ds_addr;         \
+       bus_size_t __z = __rxs->rxs_dmamap->dm_segs[0].ds_len;          \
        __m->m_data = __m->m_ext.ext_buf;                               \
-       __rxd->r3 = htole32(__rxs->rxs_dmamap->dm_segs[0].ds_len);      \
-       __rxd->r2 = htole32(BUS_ADDR_LO32(__paddr));                    \
-       __rxd->r1 = htole32(BUS_ADDR_HI32(__paddr));                    \
-       __rxd->r0 = htole32(R0_OWN | R0_FS | R0_LS);                    \
-       if ((x) == MD_NRXDESC - 1) __rxd->r0 |= htole32(R0_EOD);        \
+       __rxd->r3 = htole32(__z);                                       \
+       __rxd->r2 = htole32(BUS_ADDR_LO32(__p));                        \
+       __rxd->r1 = htole32(BUS_ADDR_HI32(__p));                        \
+       __rxd->r0 &= htole32(R0_LD);                                    \
+       __rxd->r0 |= htole32(R0_OWN);                                   \
 } while (/*CONSTCOND*/0)
 
 /* memory mapped CSR register access */
@@ -574,7 +578,10 @@ static void scx_ifmedia_sts(struct ifnet
 static int mii_readreg(device_t, int, int, uint16_t *);
 static int mii_writereg(device_t, int, int, uint16_t);
 static void phy_tick(void *);
+static void dump_hwfeature(struct scx_softc *);
 
+static void stopuengine(struct scx_softc *);
+static void startuengine(struct scx_softc *);
 static void loaducode(struct scx_softc *);
 static void injectucode(struct scx_softc *, int, bus_addr_t, bus_size_t);
 
@@ -654,6 +661,8 @@ get_clk_freq(int phandle, const char *cl
        return -1;
 }
 
+#define ATTACH_DEBUG 1
+
 static const struct device_compatible_entry compat_data[] = {
        { .compat = "socionext,synquacer-netsec" },
        DEVICE_COMPAT_EOL
@@ -681,59 +690,69 @@ scx_fdt_attach(device_t parent, device_t
        bus_space_handle_t eebsh;
        bus_addr_t addr[2];
        bus_size_t size[2];
+       void *intrh;
        char intrstr[128];



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