jonathan
Mon Sep 25 00:21:03 EDT 1995
Update of /a/cvsroot/src/sys/arch/pmax/pmax
In directory pain.lcs.mit.edu:/b/tmp/cvs-serv26052

Modified Files:
	machdep.c 
Log Message:
Add fine-grain clock code  which uses the 25 MHz TURBOChannel bus-cycle
counter on 5k/240s to interpolate to microsecond-resolution clock
in microtime().  Only the "rev B" ASIC in 5k/240s is known to have
this counter; other models may or may not.  This gives microsecond
resolution at user-level, and up to 40ns resolution (modulo the
nominal 5(?) 40MHz cpu cycles for reads to complete) in the kernel.


Change the IOASIC reset function to set up the DMA mapping for the
53c94.  Allocate 16 Kbytes of DMA buffer for 53c94 ASCs under an IOASIC,
as the 3MAX baseboard and TC options  have 128 Kbytes of static
bounce buffer, and the drivers really _should_ support 16Kbyte
I/O requests. (They don't always.)

Give the LANCE a hard reset on 5k/240s, just to be on the safe side.
(the 5k/240 I use sometimes reported errors at boot time.)