--17pEHd4RhPHOinZp
Content-Type: text/plain; charset=us-ascii

On Mon, May 01, 2000 at 09:09:17AM +1000, Simon Burge wrote:

 > >   This fails miserably on my 5000/25.  Trying to run programs get segment
 > > violations very frequently.  My guess at this point is that using
 > > uncached address space to zero the page leaves non-zeroed data in the
 > > cache.  If that cached data is then used instead of the zeroed memory,
 > > things that expect the data to be zero will fail.
 > 
 > Works ok for me on an r4400 - maybe it's a MIPS1/MIPS3 thang?  If so,
 > maybe we just put

Actually, if Michael's theory is correct, this should be easy to fix.  The
attached diff might just do it, actualy.

BTW, we need to seriously revious all the cache frobbing that happens in
the MIPS pmap.  It's ... quite a mess in there.

-- 
        -- Jason R. Thorpe <thorpej@zembu.com>

--17pEHd4RhPHOinZp
Content-Type: text/plain; charset=us-ascii
Content-Description: pmap.c fix for R3000 pageidlezero
Content-Disposition: attachment; filename=foo

Index: pmap.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/mips/pmap.c,v
retrieving revision 1.95
diff -c -r1.95 pmap.c
*** pmap.c	2000/04/28 19:25:56	1.95
--- pmap.c	2000/05/01 00:42:15
***************
*** 1630,1635 ****
--- 1630,1647 ----
  		mips_flushcache_allpvh(phys);
  	}
  #endif
+ #if defined(MIPS1)
+ 	if (CPUISMIPS3 == 0) {
+ 		/* XXX FIXME -- Not very sophisticated. */
+ 		/*
+ 		 * We're about to do an uncached access to the page,
+ 		 * but that might leave any data for this page still
+ 		 * in the cache, so we need to purge it.
+ 		 */
+ 		MachFlushDCache(MIPS_K0SEG_TO_PHYS(phys), NBPG);
+ 	}
+ #endif
+ 
  	p = (int *)MIPS_PHYS_TO_KSEG1(phys);
  	end = p + PAGE_SIZE / sizeof(int);
  	/* XXX blkclr()? */

--17pEHd4RhPHOinZp--