Module Name:	syssrc
Committed By:	mjacob
Date:		Sat Feb 24 23:30:01 UTC 2001

Modified Files:
	syssrc/sys/dev/sbus: isp_sbus.c

Log Message:
Now that the underlying code for bus_dmamap_sync appears to do the
right thing, don't use the illegal and "just worked by chance" addition
of BUS_DMA_COHERENT to bus_dmamap_load_raw. There still is a necessity
to add to the architecture to allow one to hint that this should be
a cache coherent mapping.

Fix offset argument to be zero for flushing data tranfers. Kudos to Izumi
for spotting this.


To generate a diff of this commit:
cvs rdiff -r1.36 -r1.37 syssrc/sys/dev/sbus/isp_sbus.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.