Subject: CVS commit: syssrc/sys/arch/mips/mips
To: None <source-changes@netbsd.org>
From: Rafal Boni <rafal@netbsd.org>
List: source-changes
Date: 07/25/2001 02:13:34
Module Name: syssrc
Committed By: rafal
Date: Tue Jul 24 23:13:33 UTC 2001
Modified Files:
syssrc/sys/arch/mips/mips: locore_mips3.S
Log Message:
Fix bug in mips3_proc_trampoline: SR wasn't disabled on entry, allowing an
interrupt to sneak in after EXL had been set; the interrupt EPC was stale
as PC isn't saved if EXL is set, causing the eret to return to the wrong
place and leading to kernel-mode TLB misses on user addresses. The bug
was discovered by the japanese NetBSD/*mips folks and the same fix was
found independently by shinohara-san (shin@netbsd.org).
To generate a diff of this commit:
cvs rdiff -r1.69 -r1.70 syssrc/sys/arch/mips/mips/locore_mips3.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.