Module Name:	syssrc
Committed By:	thorpej
Date:		Tue Nov 13 19:49:13 UTC 2001

Modified Files:
	syssrc/sys/arch/algor/algor [thorpej-mips-cache]: bus_dma.c
	syssrc/sys/arch/arc/arc [thorpej-mips-cache]: bus_dma.c
	syssrc/sys/arch/pmax/pmax [thorpej-mips-cache]: bus_dma.c

Log Message:
For the virtually-indexed write-back cache dmamap_sync:

Note that we can only use Inv on PREREAD if the buffer
start/end are cacheline-aligned.  If they're not, we
need to use WB_Inv, otherwise we can end up trashing
someone else's data.

XXX For now, simply use WB_Inv for the PREREAD case
always.  I will make some other changes later that
will enable the dmamap_sync routine to easily determine
if it's safe to use Inv.

Many thanks to Michael Hitch for tracking this down.


To generate a diff of this commit:
cvs rdiff -r1.4.2.1 -r1.4.2.2 syssrc/sys/arch/algor/algor/bus_dma.c
cvs rdiff -r1.10.2.1 -r1.10.2.2 syssrc/sys/arch/arc/arc/bus_dma.c
cvs rdiff -r1.32.2.2 -r1.32.2.3 syssrc/sys/arch/pmax/pmax/bus_dma.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.