Re: CVS commit: syssrc/sys/arch/arm/sa11x0

[IWAMOTO Toshihiro <iwamoto%sat.t.u-tokyo.ac.jp@localhost>]

At Tue, 13 Aug 2002 01:26:42 +0300 (EEST),
Robert Swindells wrote:
> 
> 
> Module Name:  syssrc
> Committed By: rjs
> Date:         Mon Aug 12 22:26:42 UTC 2002
> 
> Modified Files:
>       syssrc/sys/arch/arm/sa11x0: sa1111.c
> 
> Log Message:
> Always clear SA11x0 GPIO in interrupt handler.
> 
> 
> To generate a diff of this commit:
> cvs rdiff -r1.4 -r1.5 syssrc/sys/arch/arm/sa11x0/sa1111.c
> 
> Please note that diffs are not public domain; they are subject to the
> copyright notices on the relevant files.


I think this change will cause unnecessary interrupts if there are
more than one interrupt.  IMO, what should be done here is:

1. Read SACCIC_INTSTATCLR0, SACCIC_INTSTATCLR1.
2. If no bits are set, clear the SA11x0 gpio interrupt and reread
SACCIC_INTSTATCLR[01] to see if any bits are set.  If no bits are
set, return.
3. Process interrupts.  Clear the gpin interrupt before processing the
last one.

--
IWAMOTO Toshihiro