CVS commit: syssrc/sys/arch/sh5/sh5

[Steve Woodford <scw%netbsd.org@localhost>]

Module Name:    syssrc
Committed By:   scw
Date:           Tue Sep 10 12:27:22 UTC 2002

Modified Files:
        syssrc/sys/arch/sh5/sh5: exception.S

Log Message:
 - Remove the RESVEC vector table (panic/debug traps). It's now in
   machine-specific code.

 - Re-work the code which detects a nested critical section event.
   We can now determine who is the owner of the critical section, and
   what event occurred while it was owned.

 - Work-around a silicon bug which can cause a nested critical event.
   In the _EXCEPTION_ENTRY() macro (which sets up the critical section),
   if there is a pending hardware interrupt which has a higher priority
   than the current IMASK, then the "putcon" which supposedly clears SR.BL
   and sets SR.IMASK to 0xf is not atomic. The pending hardware interrupt
   will be taken, causing a nested critical section event. The work-around
   is to update SR.BL and SR.IMASK separately using two "putcon" insns.


To generate a diff of this commit:
cvs rdiff -r1.12 -r1.13 syssrc/sys/arch/sh5/sh5/exception.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.