CVS commit: syssrc/sys/arch/mips

[Simon Burge <simonb%netbsd.org@localhost>]

Module Name:    syssrc
Committed By:   simonb
Date:           Sun Nov 24 07:41:31 UTC 2002

Modified Files:
        syssrc/sys/arch/mips/include: cache_mipsNN.h
        syssrc/sys/arch/mips/mips: cache.c cache_mipsNN.c

Log Message:
New generic way-aware MIPS32/64 range-index cache functions with proper
handling for phyiscally-indexed caches where the way size is greater than
the page size.
These work fine with pass 1 SB1 cores, so g/c those workarounds.

Much thanks to Chris Demetriou for many suggestions and helping me get
my head around all this.


To generate a diff of this commit:
cvs rdiff -r1.2 -r1.3 syssrc/sys/arch/mips/include/cache_mipsNN.h
cvs rdiff -r1.13 -r1.14 syssrc/sys/arch/mips/mips/cache.c
cvs rdiff -r1.5 -r1.6 syssrc/sys/arch/mips/mips/cache_mipsNN.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.