Module Name:	syssrc
Committed By:	simonb
Date:		Tue Dec 17 12:07:51 UTC 2002

Modified Files:
	syssrc/sys/arch/mips/mips: mips_machdep.c

Log Message:
Mark the Au1x00 CPUs as having a fully coherent data cache that doesn't
require flushing (even in the instruction cache handlers).  This gives
about a 4% improvement in a "make depend" benchmark.

Mark the SB-1 CPUs as having a fully coherent data cache that only
require flushing in the instruction cache handlers.  This gives about
a 5% improvement in a "make depend" benchmark.


To generate a diff of this commit:
cvs rdiff -r1.155 -r1.156 syssrc/sys/arch/mips/mips/mips_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.