Subject: Re: CVS commit: src/sys/dev/pci
To: None <lha@netbsd.org>
From: Izumi Tsutsui <tsutsui@ceres.dti.ne.jp>
List: source-changes
Date: 01/04/2003 13:51:58
In article <20030103190110.58316B42C@cvs.netbsd.org>
lha@netbsd.org wrote:
> Modified Files:
> src/sys/dev/pci: if_vr.c if_vrreg.h
>
> Log Message:
> From freebsd if_vr.c:1.43,1.56 and if_vrreg.h:1.11,1.14
>
> - Windows put the chip in suspended mode, make sure we unsuspend
> it. 1.43, by Takefumi SAYO <stake@po.shiojiri.ne.jp>
>
> - Detect the revision of the Rhine chip we're using, and force reset
> when the chip supports it. 1.65, by silby@freebsd.org
It's better to use common macros in pcireg.h:
Index: if_vr.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/if_vr.c,v
retrieving revision 1.59
diff -u -r1.59 if_vr.c
--- if_vr.c 2003/01/03 19:01:09 1.59
+++ if_vr.c 2003/01/04 04:42:32
@@ -1411,7 +1411,7 @@
struct pci_attach_args *pa = (struct pci_attach_args *) aux;
bus_dma_segment_t seg;
struct vr_type *vrt;
- u_int32_t command;
+ u_int32_t pmreg, reg;
struct ifnet *ifp;
u_char eaddr[ETHER_ADDR_LEN];
int i, rseg, error;
@@ -1433,38 +1433,39 @@
* Handle power management nonsense.
*/
- command = PCI_CONF_READ(VR_PCI_CAPID) & 0x000000FF;
- if (command == 0x01) {
- command = PCI_CONF_READ(VR_PCI_PWRMGMTCTRL);
- if (command & VR_PSTATE_MASK) {
+ if (pci_get_capability(pa->pa_pc, pa->pa_tag,
+ PCI_CAP_PWRMGMT, &pmreg, 0)) {
+ reg = PCI_CONF_READ(pmreg + PCI_PMCSR);
+ if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) {
u_int32_t iobase, membase, irq;
/* Save important PCI config data. */
iobase = PCI_CONF_READ(VR_PCI_LOIO);
membase = PCI_CONF_READ(VR_PCI_LOMEM);
- irq = PCI_CONF_READ(VR_PCI_INTLINE);
+ irq = PCI_CONF_READ(PCI_INTERRUPT_REG);
/* Reset the power state. */
printf("%s: chip is in D%d power mode "
- "-- setting to D0\n",
- sc->vr_dev.dv_xname, command & VR_PSTATE_MASK);
- command &= 0xFFFFFFFC;
- PCI_CONF_WRITE(VR_PCI_PWRMGMTCTRL, command);
+ "-- setting to D0\n",
+ sc->vr_dev.dv_xname, reg & PCI_PMCSR_STATE_MASK);
+ reg = (reg & ~PCI_PMCSR_STATE_MASK) |
+ PCI_PMCSR_STATE_D0;
+ PCI_CONF_WRITE(pmreg + PCI_PMCSR, reg);
/* Restore PCI config data. */
PCI_CONF_WRITE(VR_PCI_LOIO, iobase);
PCI_CONF_WRITE(VR_PCI_LOMEM, membase);
- PCI_CONF_WRITE(VR_PCI_INTLINE, irq);
+ PCI_CONF_WRITE(PCI_INTERRUPT_REG, irq);
}
}
/* Make sure bus mastering is enabled. */
- command = PCI_CONF_READ(PCI_COMMAND_STATUS_REG);
- command |= PCI_COMMAND_MASTER_ENABLE;
- PCI_CONF_WRITE(PCI_COMMAND_STATUS_REG, command);
+ reg = PCI_CONF_READ(PCI_COMMAND_STATUS_REG);
+ reg |= PCI_COMMAND_MASTER_ENABLE;
+ PCI_CONF_WRITE(PCI_COMMAND_STATUS_REG, reg);
/* Get revision */
- sc->vr_revid = PCI_CONF_READ(VR_PCI_REVID) & 0x000000FF;
+ sc->vr_revid = PCI_REVISION(pa->pa_class);
/*
* Map control/status registers.
Index: if_vrreg.h
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/if_vrreg.h,v
retrieving revision 1.10
diff -u -r1.10 if_vrreg.h
--- if_vrreg.h 2003/01/03 19:01:09 1.10
+++ if_vrreg.h 2003/01/04 04:42:32
@@ -365,34 +365,7 @@
* other PCI registers.
*/
-#define VR_PCI_VENDOR_ID 0x00
-#define VR_PCI_DEVICE_ID 0x02
-#define VR_PCI_COMMAND 0x04
-#define VR_PCI_STATUS 0x06
-#define VR_PCI_REVID 0x08
-#define VR_PCI_CLASSCODE 0x09
-#define VR_PCI_LATENCY_TIMER 0x0D
-#define VR_PCI_HEADER_TYPE 0x0E
#define VR_PCI_LOIO 0x10
#define VR_PCI_LOMEM 0x14
-#define VR_PCI_BIOSROM 0x30
-#define VR_PCI_INTLINE 0x3C
-#define VR_PCI_INTPIN 0x3D
-#define VR_PCI_MINGNT 0x3E
-#define VR_PCI_MINLAT 0x0F
#define VR_PCI_RESETOPT 0x48
#define VR_PCI_EEPROM_DATA 0x4C
-
-/* power management registers */
-#define VR_PCI_CAPID 0xDC /* 8 bits */
-#define VR_PCI_NEXTPTR 0xDD /* 8 bits */
-#define VR_PCI_PWRMGMTCAP 0xDE /* 16 bits */
-#define VR_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */
-
-#define VR_PSTATE_MASK 0x0003
-#define VR_PSTATE_D0 0x0000
-#define VR_PSTATE_D1 0x0002
-#define VR_PSTATE_D2 0x0002
-#define VR_PSTATE_D3 0x0003
-#define VR_PME_EN 0x0010
-#define VR_PME_STATUS 0x8000
---
Izumi Tsutsui
tsutsui@ceres.dti.ne.jp