In message <20031007160309.DB08D2DA1D@cvs.netbsd.org>, you write: 

-> Module Name:	src
-> Committed By:	tsutsui
-> Date:		Tue Oct  7 16:03:09 UTC 2003
-> 
-> Modified Files:
-> 	src/sys/arch/sgimips/include: bus.h
-> 	src/sys/arch/sgimips/sgimips: bus.c
-> 
-> Log Message:
-> Use proper mips_dcache_{wb,inv,wbinv}_range() ops in dmamap sync function
-> if possible. Tested on my O2 (with r5ksc patch).
-> 
-> XXX should we apply similar changes to mips/bus_dma.c and use it?

Hmm, I'm interested in how you found this and/or how it manifested itself.
I had lots and lots of cache-looking problems with the Intel GigE card in
my O2 and trying the obvious things (using the generic arch/mips/mips/bus_
dma.c code, disabling L2) didn't make it go away.  I guess I should give
it a try again.

Thanks again for all the work, I think I owe you a few {beers/cookies/
whatever else one can bribe you with :-)

--rafal

----
Rafal Boni                                                     rafal@pobox.com
  We are all worms.  But I do believe I am a glowworm.  -- Winston Churchill