On 29-Oct-2006 Izumi Tsutsui wrote:
> But I don't know the way how to determine possible maximum cacheline
> size at compile time because cache design could be configurable.
> Some sgimips machines could have 128 bytes, but HPPA machines
> might have larger one. Do you have any good idea how to implement it?
> Check it at runtime and calculate offsets dynamically?

For the POWER chips, certain versions had different cacheline sizes from chip
to chip.  There is an asm op to determine the cacheline size.  We could make a
getcachelinesize() function, but I don't think we can hardcode it at compile
time.

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Tim Rightnour <root@garbled.net>
NetBSD: Free multi-architecture OS http://www.netbsd.org/
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