On Nov 2, 2006, at 1:27 AM, David Young wrote:

> There are also chips that let us write a register to set the  
> descriptor
> size to whatever we like.

Yes, that is useful.

> For all other chips, we either need for the platform to ensure DMA
> coherency, or else we need to arrange exclusive host/device access to
> every N descriptors, where (N * sizeof(descriptor)) % sizeof 
> (cacheline)
> == 0, or else something else....

...and that should be fairly easy, since descriptors tend to be sized  
in powers-of-two.

> Suppose I add #define bus_dma_cacheline(__tag) in an MI header,  
> setting it
> to some Suitably Large number (128? 256?), and then let MD code  
> override?
> E.g., MI:
>
>         #define bus_dma_cacheline(__tag)        ((bus_size_t)256)
>
> MD:
>
>         static inline bus_size_t
>         _myarch_bus_dma_cacheline(bus_dma_tag_t tag)
>         {
>                 /* ... */
>         }
>         #undef bus_dma_cacheline
>         #define bus_dma_cacheline       _myarch_bus_dma_cacheline
>
> On coherent architectures such as x86, should bus_dma_cacheline()
> yield the actual cacheline size, or 1?  If 1, what should the name of
> the function be?

Uh, let's not do that... I will work on this issue evenings this week  
and post a diff.

-- thorpej