CVS commit: [netbsd-10] src/sys/arch/powerpc/pic

["Martin Husemann" <martin%netbsd.org@localhost>]

Module Name:    src
Committed By:   martin
Date:           Sat Feb 22 12:27:48 UTC 2025

Modified Files:
        src/sys/arch/powerpc/pic [netbsd-10]: intr.c picvar.h

Log Message:
Pull up following revision(s) (requested by jmcneill in ticket #1056):

        sys/arch/powerpc/pic/intr.c: revision 1.35
        sys/arch/powerpc/pic/intr.c: revision 1.36
        sys/arch/powerpc/pic/intr.c: revision 1.37
        sys/arch/powerpc/pic/picvar.h: revision 1.14

powerpc: Fix ci_ipending corruption with cascaded pics
A cascaded pic will register pic_handle_intr as its interrupt handler,
but interrupt handlers are called with MSR[EE] = 1. This breaks
assumptions in pic callbacks and can result in eg. corrupt ci_ipending
due to a read/modify/write of the field with nested interrupts.

Fix this by always clearing MSR[EE] at the top of pic_handle_intr.

powerpc: Mask interrupts after returning from handler.
Now that we are explicitly masking interrupts on entry of pic_handle_intr,
we need to disable (instead of store) interrupts after calling
intr_deliver.

powerpc: Don't enable interrupts before calling cascaded intr handler.
Before calling a normal interrupt handler, the pic code adjusts cpl and
enables interrupts. Don't do this with interrupt sources that feed
cascaded pics as the resulting handler will do it anyway, and it can
result in multiple interrupts firing on the parent pic just to service
a single interrupt on the child.


To generate a diff of this commit:
cvs rdiff -u -r1.34 -r1.34.4.1 src/sys/arch/powerpc/pic/intr.c
cvs rdiff -u -r1.13 -r1.13.16.1 src/sys/arch/powerpc/pic/picvar.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.