Greetings to the list,

Has anyone came across of the below behaviour ?

The platform I use for a project is a TS7200, based around the cirrus
logic EP3902.
The SBC has a PC104 expansion connector. On the connector sits a 12
bit ADC board of the same company...

Small programs that initiate a single ADC conversion work like a dream..
My problem starts when I want to pool data at higher speeds...
I have not been able to go above 30 samples/sec.

The SBC runs a kernel compiled from CVS some weeks ago.
Do I need to tweak the kernel files in some point ?
Or this is the higher speed that a userland program can go ?

Should I try to write a driver to achieve the speed I want ? 50Ksps
would be OK for me..
The manufacture company says that 100Ksps are feasible...and the ADC
chip can do 125Ksps



below is the code that I am testing.. it is quite small
The time that elapses between the printfs` is 1 sec


Any suggestions, recommendations would be greatly appreciated

Regards,
Christos

----------------------------
#include <stdio.h>
#include <fcntl.h>
#include <sys/time.h>
#include <sys/mman.h>


int main(){
int i;
int k;
volatile unsigned short *RESULT_REG;
volatile unsigned char *base;
volatile short *iptr;
iptr =3D (short *)malloc(sizeof(int));

int fd =3D open("/dev/mem", O_RDWR);
base =3D mmap(0, getpagesize(), PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0x11C=
00160 )
;
i =3D 0;

RESULT_REG =3D (unsigned short *)(base + 0x02); // two byte read

printf("Start loop\n");
*base =3D 0x00; //initiate a conversion on ch 0

usleep(10); //wait for conversion to finish

while (( *base & 0x80 ) && ( i < 30 )) { //check if bit 7 of the base
R/W register is set andcheck the loop count
        iptr[i] =3D *RESULT_REG; //save the data
        *base =3D 0x00; //initiate a new conversion on adc ch 0
        i++;
        usleep(10);
        }



printf("End loop\n");

k =3D 0;
while ( k < 30){

printf("%x\n", iptr[k]);
k++;
}

return(0);
}