Hello,

# Jim Higgins 2006-11-28:
> PPCBoot 2.0.0 (Dec  5 2003 - 14:57:54)
> 
> CPU:   IBM PowerPC 405EP? (PVR=51210950) at 266.333 MHz (PLB=133, 
> OPB=66, EBC=44 MHz)
>            16 kB I-Cache 16 kB D-Cache

The bootloader gets the cache right ...

> cpu0 at plb0: 266MHz Version 0x5121 (Revision 9.80)
> Instruction cache size 0 line size 4
> Data cache size 0 line size 4

... while the kernel is not. A case statement for the 405EP in

  sys/arch/powerpc/ibm4xx/cpu.c:cpu_probe_cache()

should solve the problem. The system really can't live without knowing
cache size & cacheline size, the code in -current will even panic() if
it can't fill meaningful cache params.

Hope this helps,
	-- Jachym

BTW: port-powerpc@ might be a better list to discuss this.