A note on NAND CLE/ALE wiring;

It's very benefitial to have CLE/ALE signal lines tied with
(SRAM) memory controller's address signal.  The practice will
reduce programming burden significantly since CLE / ALE
fiddling can be done to perform write on alias'ed address of
the data xfering byte.  The following segment is to read NAND
prodID;

        nand[4] = 0x90;
        nand[8] = 0x00;
        v0 = nand[0] << 8;
        v0 |= nand[0];                  /* 16bit product ID maker:device */
        return v0;

Here, offset [4] is for command notify, and [8] is for address notify.

Not all memory controller will allow the solution but useful for most
of modern SoC I believe.

Toru Nishimura/ALKYL Technology