Jan-Simon Pendry writes:
: unless you redesign the interrupt mechanism, you still have to
: raise spl levels for locks on data structures that can be accessed
: from interrupt handlers (or timeouts etc).  if the cpu runs at the
: normal spl, it may end up taking an interrupt and then trying to
: lock a structure that the interrupted thread on the cpu had already
: locked.

this is, of course, true.  the problem with this approach on many x86
implementations, where raising the spl level means re-programming the
pic masks, is that fiddling with the pic is expensive (as bruce
mentioned a while ago).  now it's happening all the more often,
potentially unnecessarily (if you don't take an interrupt in the time
that you hold the lock then the pic twiddling was wasted).  intel did
some interesting work on a soft-spl scheme where the actually pic
fiddling was deferred until the interrupt actually arrived.  an
implementation of this scheme for unixware exists, and can produce
performance noticable improvements in many situations.

another problem with this, when combined with `time to market'
pressures, is that the decisions about what spl level to use with any
lock is apparently easy, but often botched.  as a hard example, sco's
openserver typically raises the spl level to 7 (the highest, which
blocks everything) on _all_ lock acquisitions.  this causes dire
interrupt starvation, and hits 8250 serial stuff like a hammer (ever
try getting reasonble serial performance from a dual 486 or pentium
system running our mpx 3.0 release ?).