I noticed this several years ago.  At the time I investigated it, we
did not support any CPU types on which we switched to the inferior
without -- in some fashion or other -- having done a cache
synchronization.  I documented the behavior on one of the mailing
lists.

One thing to note is that, since PT_WRITE_[ID] is actually done in the
debugger process now (rather than switching to the inferior process,
as in the old mechanism), the constraints are a little different.  It
occurs to me now that this behavior could cause a significant slowdown
on platforms using a VAC; mapping the page into the kernel will cause
an alias and therefore disable caching, but I don't think unmapping it
will will reenable caching in all of the pmaps.