On Mon, 15 Mar 1999, Jonathan Stone wrote:

> But sounds like you're tuning for VACs which dont have adequate
> hardware ASID support, so you have to flush the entire cache on
> every context-switch. Is that right?

If your VAC has no ASID support you have several additional problems
depending on the md VM implementation.  First, this only works if the
kernel address space does not overlap the user address space, otherwise
there's no way to identify cached user data from cached kernel data (not
really an issue with the MIPS MMU design, is it?)  Also, if any PROM code
needs to be executed you have the same problem.  And if it's a writeback
cache, the cache must by flushed before mappings are removed from the MMU.
I'd hate to think of what would happen if the page scanner demaps a page
that the VAC has dirty data for....

=========================================================================
Eduardo Horvath				eeh@one-o.com
	"I need to find a pithy new quote." -- me