Jonathan Stone wrote:

> Thats not what I meant. My understanding, from previous discussions
> with Mark, is that some ARM cores (strongarm) have ASIDs and selective
> flush for dat references, but do not have selective (by ASID) for the
> I-cache.  On context switch, you gotta flush the entire I-cache.

In that case, Mark was wrong ;-) None of the ARM cores have ASIDs for
data or address references, but some have selective cache invalidation
(of varying levels of usefulness). In fact the StrongARM SA1100 has some
basic ASID support, but it's too much of a bodge to be useful. My
original discussion was meant to be CPU-indepenadant though :)

	Neil