Easy question: if you're at a spl which has interrupts disabled, should
spl0() enable them? I would think so, but the MIPS port is a little
diferent. With MIPS, there are bits to block each individual interrupt
line, but there's also a single bit to enable/disable them all.

	Any opinions on whether spl0() should, at the same time it enables all
the individual interrupt lines, should also set the overall-enable bit?
Given that there's no other standard mechanism in place that would
enable it.

	The context of my question is that I have a kernel thread, which seems
to be created at splhi() (which seems strange and could form another
question in and of itself). Since I have never been at a lower spl to
splx() back to, the only way to lower my priority seems to be a spl0().
But it doesn't actually set the enable-interrupts bit, so it isn't
enough.

	Thanks!
	-- Ethan