On Mon, Feb 26, 2001 at 01:39:48PM -0800, Matthew Jacob wrote:
> I still would have to change the sparc64 implementation to grok this I
> believe. Note that BUS_DMA_COHERENT for bus_dmamem_map means make the
> CPU's view coherent (i.e., set PG_NVC (no vcache)) of memory. There's no tying
> this to setting iommu TTE bits.

Ha OK, on sparc64 we have two places to deal with: CPU<->Memory and
Memory<->device, which have each their own cache, rigth ?
I still believe that memory bus_dmamem_map()'ed BUS_DMA_COHERENT should be
from CPU to device (and vice-versa), so both caches should be configured for
this.

> 
> And lacking any architectural *requirement* for requiring such ordering, in
> fact, I'd rather have a big fat rule breakage with a comment than things just
> working because the order of function calls makes things work.

Hum, you're rigth. For me it was obvious that a DMA map should be mapped before
loaded but this is definitively 2 different things.
So maybe we need to handle BUS_DMA_COHERENT in bus_dmamap_load* too, but
the behavior needs to be clearly specified before, and documentation updated
at the same time.

--
Manuel Bouyer, LIP6, Universite Paris VI.           Manuel.Bouyer@lip6.fr
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