Subject: bus_dma, the next chapter...
To: None <tech-kern@netbsd.org>
From: Matthew Jacob <mjacob@feral.com>
List: tech-kern
Date: 02/27/2001 15:11:18
so in my quest to DTRT with BusDma, I changed the PCI code to
use bus_dmamap_load_raw as the SBus code was changed to do- after
all- if it is right for one, it must be right for another.

Tsk.

NetBSD 1.5S (ALPHA-$Revision: 1.145 $) #19: Tue Feb 27 14:46:01 PST 2001
    mjacob@nobble.feral.com:/tstsys/arch/alpha/compile/MJACOB
Digital AlphaPC 164 500 MHz, s/n 
8192 byte page size, 1 processor.
total memory = 128 MB
(2472 KB reserved for PROM, 125 MB used by NetBSD)
avail memory = 109 MB
using 816 buffers containing 6528 KB of memory
mainbus0 (root)
cpu0 at mainbus0: ID 0 (primary), 21164A-2
cpu0: Architecture extensions: 1<BWX>
cpu0: VAX FP support, IEEE FP support, Primary Eligible
cia0 at mainbus0: DECchip 2117x Core Logic Chipset (ALCOR/ALCOR2), pass 3
cia0: extended capabilities: 21<DWEN,BWEN>
cia0: using BWX for PCI config access
pci0 at cia0 bus 0
pci0: i/o space, memory space enabled, rd/line, rd/mult, wr/inv ok
de0 at pci0 dev 5 function 0
de0: interrupting at eb164 irq 2
de0: 21140A [10-100Mb/s] pass 2.0
de0: address 00:40:05:2d:96:40
isp0 at pci0 dev 6 function 0
isp0: Qlogic ISP Driver, NetBSD (pci) Platform Version 1.1 Core Version 2.0
isp0: interrupting at eb164 irq 0
isp0: Differential Mode
isp0: Ultra Mode Capable
isp0: Board Revision 1040B, loaded F/W Revision 4.66.0
isp0: Last F/W revision was 4.66.0
isp0: 848 max I/O commands supported
panic: _bus_dmamap_load_raw_direct: not implemented


So- if we have an architecture that requires the use of bus_dmamap enad
bus_dmamap_load and so on, all architectures should be a bit more complete.
This would be more worthwhile pursuing than a dreamcast port or a __P hunt
(IMO).

-matt