Hi,

       From: Manuel Bouyer <bouyer@antioche.lip6.fr>
    Subject: Re: help with pci/pci bridges
      Date : Mon, 24 Jun 2002 16:46:06 +0200
 Message-ID: <20020624164606.A16537@antioche.lip6.fr>

$ Do you know if it's part of the standart PCI/PCI bridge resister set ?

My knowledge is about PCI-CardBus bridge.
According to sys/dev/pci/pccbbreg.h, PCI_BCR_INTR(0x3c) has this bit.

/* PCI_BCR_INTR bits for generic PCI-CardBus bridge */
#define CB_BCR_RESET_ENABLE     0x00400000
#define CB_BCR_INTR_IREQ_ENABLE 0x00800000
#define CB_BCR_PREFETCH_MEMWIN0 0x01000000
#define CB_BCR_PREFETCH_MEMWIN1 0x02000000
#define CB_BCR_WRITE_POST_ENABLE 0x04000000 

According to sys/dev/pci/ppbbreg.h, PCI-PCI bridge has bridge control 
register.

/*
 * bridge control register (see table 3.9 of ppb rev. 1.1)
 *
 * Note these are in the *upper* 16 bits if the Bridge Control
 * Register (the bottom 16 are Interrupt Line and Interrupt Pin).
 */
#define PPB_BC_BITBASE                     16

#define PPB_BC_PARITYERRORRESPONSE_ENABLE  (1U << (0 + PPB_BC_BITBASE))
#define PPB_BC_SERR_ENABLE                 (1U << (1 + PPB_BC_BITBASE))
#define PPB_BC_ISA_ENABLE                  (1U << (2 + PPB_BC_BITBASE))
#define PPB_BC_VGA_ENABLE                  (1U << (3 + PPB_BC_BITBASE))
#define PPB_BC_MASTER_ABORT_MODE           (1U << (5 + PPB_BC_BITBASE))
#define PPB_BC_SECONDARY_RESET             (1U << (6 + PPB_BC_BITBASE))
#define PPB_BC_FAST_B2B_ENABLE             (1U << (7 + PPB_BC_BITBASE))
        /* PCI 2.2 */
#define PPB_BC_PRIMARY_DISCARD_TIMEOUT     (1U << (8 + PPB_BC_BITBASE))
#define PPB_BC_SECONDARY_DISCARD_TIMEOUT   (1U << (9 + PPB_BC_BITBASE))
#define PPB_BC_DISCARD_TIMER_STATUS        (1U << (10 + PPB_BC_BITBASE))
#define PPB_BC_DISCARD_TIMER_SERR_ENABLE   (1U << (11 + PPB_BC_BITBASE))


I think PPB_BC_FAST_B2B_ENABLE is "write post enable".
Regards
---
 Masanori Kanaoka	kanaoka@ann.hi-ho.ne.jp