In sys/arch/evbmips/include/intr.h, we have:

	#define IST_UNUSABLE    -1      /* interrupt cannot be used */
	#define IST_NONE        0       /* none (dummy) */
	#define IST_PULSE       1       /* pulsed */
	#define IST_EDGE        2       /* edge-triggered */
	#define IST_LEVEL       3       /* level-triggered */

which gets used in sys/arch/mips/alchemy/au_icu.c to configure
an interrupt line as level triggered but it assumes that the
interrupt is active high.  However, on the Alchemy au1500, the
USB Host controller is level triggered, active low.  Since 
IST_LEVEL currently assumes "active high", this screws me.
 
So I propose (as per suggestion of Christos):
 
-  Add the following:
        #define IST_HIGH        0       /* active high */
        #define IST_LOW         0x1000  /* active low */
 
- In au_icu.c:

===================================================================
RCS file: /cvsroot/src/sys/arch/mips/alchemy/au_icu.c,v
retrieving revision 1.4
diff -r1.4 au_icu.c
272,274c272,280
<                       REGVAL(icu_base + IC_CONFIG2_SET) = irq;
<                       REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq;
<                       REGVAL(icu_base + IC_CONFIG0_SET) = irq;
---
>                       if (type&IST_LOW) {     /* active low */
>                               REGVAL(icu_base + IC_CONFIG2_SET) = irq;
>                               REGVAL(icu_base + IC_CONFIG1_SET) = irq;
>                               REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq;
>                       } else {    /* else active high */
>                               REGVAL(icu_base + IC_CONFIG2_SET) = irq;
>                               REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq;
>                               REGVAL(icu_base + IC_CONFIG0_SET) = irq;
>                       }


This way, it doesn't affect code in other areas but accomodates
active high and active low interrupts.

constructive comments?


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