Subject: RE: random core dumps while swapping
To: 'David Laight' <david@l8s.co.uk>
From: Huy Vu <hvu@hyperchip.com>
List: tech-kern
Date: 03/17/2003 17:35:39
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> I'm running 'current' as of this morning....
Our snap shot of CVS is from the 1.6 branch dated November 20, 2002
> Core was generated by `sleep'.
> Program terminated with signal 10, Bus error.
I do not think that it matters what generated coredump. My theory is that
UVM trashes the memory pages causing protection problems. So whatever is
loaded into memory, if the memory pages are screwed up the systom will be
random coredumps.
Maybe some UVM experts may shed some light into this phenomenon!
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<P><FONT SIZE=3D2>> I'm running 'current' as of this =
morning....</FONT>
</P>
<P><FONT SIZE=3D2>Our snap shot of CVS is from the 1.6 branch dated =
November 20, 2002</FONT>
</P>
<P><FONT SIZE=3D2>> Core was generated by `sleep'.</FONT>
<BR><FONT SIZE=3D2>> Program terminated with signal 10, Bus =
error.</FONT>
</P>
<P><FONT SIZE=3D2>I do not think that it matters what generated =
coredump. My theory is that UVM trashes the memory pages causing =
protection problems. So whatever is loaded into memory, if the =
memory pages are screwed up the systom will be random coredumps. =
</FONT></P>
<P><FONT SIZE=3D2>Maybe some UVM experts may shed some light into this =
phenomenon!</FONT>
</P>
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