I recently had some problems with "atactl smart status" on a big-endian
system. The drive rejected the command, and I tried to figure out why.

I noticed that, in atactl.c, the magic number for the SMART command
is always set as a little-endian value:

	req.cylinder = htole16(WDSMART_CYL);

Where WDSMART_CYL is 0xc24f.

However, that doesn't seem correct to me. Reading the ATA spec, it
simply requires that "LBA mid" (cyl_lo) and "LBA high" (cyl_hi)
are 0x4f and 0xc2 respectively. If you follow the path of the
r_cylinder value as passed in through the ATAIOCCOMMAND, it will
always be assigned as:

	cyl_lo = cyl;
	cyl_hi = cyl >> 8;

In other words, native byte order is the right way to go, and atactl.c
should be changed.

I'll make this change in a few days if there are no objections.

- Frank