On Jan 9, 2006, at 6:28 AM, Wolfgang Solfrank wrote:

>>> Concrete example: wi(4) on mips.  Currently these just "work"  
>>> because the PCI space is mapped uncached.  But the barrier ops  
>>> for that platform issues a cache flush.
>
> The above is _not_ valid in all cases.  E.g. on PowerPC, the cpu  
> will reorder
> bus cycles even to uncached regions of its bus space.  You have to  
> explicitly
> use barrier instructions to forbid reordering across these borders.

Alpha is the same way with regard to barriers.  Barriers have nothing  
to do with caching, and everything to do with the order in which bus  
cycles are issued.

Alpha is even more "strange".  For non-prefetchable devices, sparse  
space must be used[*].  Whether a device is prefetchable or not  
depends on the device (there is a bit in the PCI configuration header  
for it, and it applies to memory-mapped devices only, not I/O-mapped).

[*] Except on systems that have BWX and a similarly-capable bus  
controller.

-- thorpej